SV Compilation error: Unexpected token integer

Question

I am compiling the below system verilog code in Active-HDL9.1 simulator. When compile i get this error

Error: VCP2000 tb_hutil.sv : (35, 15): Syntax error. Unexpected token: integer[_INTEGER]. Expected tokens: 'constraint'.

package hutil_pkg;
`define DATE "June_2012"
`ifdef TBID
`else
  `define TBID "rapidio2_testbench"
`endif

`ifdef AUTHOR
`else
  `define AUTHOR "ALTERA"
`endif


`define INFO     32'h00000001
`define DEBUG    32'h00000002
`define WARNING  32'h00000004
`define FAILURE  32'h00000008

static integer err_cnt;          //Line no.35 //error on this line

I don't understand this error and no idea whether the problem is with system verilog syntax or tool issues.

Answer 1

In the posted example an endpackage is missing. Also you could use `ifndef for you if not defined statments.

Example below compiles on EDA Playground:

package hutil_pkg;
`define DATE "June_2012"
`ifndef TBID
  `define TBID "rapidio2_testbench"
`endif

`ifndef AUTHOR
  `define AUTHOR "ALTERA"
`endif

`define INFO     32'h00000001
`define DEBUG    32'h00000002
`define WARNING  32'h00000004
`define FAILURE  32'h00000008

static integer err_cnt; 

endpackage