Synthesis of two simulation identical designs - with and without second if in process for SET clk

Question

I have got two identical (by means of simulation) flip flop process in verilog.

First is just a standard description of register with asynchronous reset (CLR) and clock (SET) with data in tied to 1:

always @(posedge SET, posedge CLR)
if (CLR)
    Q <= 0;
else
    Q <= 1;

second one is the same as above but with second if condition for SET signal:

always @(posedge SET, posedge CLR)
if (CLR)
    Q <= 0;
else if (SET)
    Q <= 1;

There is no differences between these two implementations of flip-flop in simulation. But what does the verilog standard says about this cases? Should these tests be equivalent as well as their netlists after synthesis process?

Answer 1

The "if (SET)" in your second example is redundant and would be optimized away n synthesis. Since the always block will only be entered on a posedge of SET or CLR, the else statement implies that a posedge of SET has occurred.

Incidentally, the first example is a much more accepted version for coding flip flops. I've yet to see the second version make it into a shipping design.