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20
Devhide
2025-01-01 18:26:52
1k
Views
VHDL: Internal signal in component not triggered
Published on
01 January 2025 at 18:26
#vhdl
#vivado
365
Views
What is the cause of Vivados 'synth 8-1027' error?
Published on
01 January 2025 at 18:26
#vhdl
#fpga
#xilinx
#vivado
5.2k
Views
Error synthesizing hierarchical names in vivado
Published on
01 January 2025 at 18:26
#verilog
#fpga
#system-verilog
#xilinx
#vivado
119
Views
NEXYS 4: Signal Disappearing Across Wire in Port Instantiation
Published on
30 December 2024 at 21:11
#port
#verilog
#instantiation
#vivado
2.8k
Views
Assign reg which has initial value
Published on
04 December 2024 at 16:00
#verilog
#fpga
#system-verilog
#vivado
9.9k
Views
What is "top-level HDL wrapper" means in Vivado SoC?
Published on
03 January 2025 at 04:48
#vhdl
#vivado
#soc
587
Views
Verilog: Does Vivado Synthesis tool, add signals to sensitivity list automatically?
Published on
03 January 2025 at 00:25
#verilog
#synthesis
#vivado
810
Views
Scaling down a 128 bit Xorshift. - PRNG in vhdl
Published on
04 December 2024 at 16:05
#random
#vhdl
#vivado
2.3k
Views
How to use GHDL to simulate generated XilinX IP?
Published on
04 December 2024 at 16:07
#vhdl
#xilinx
#vivado
255
Views
mex.h header bugs in Vivado HLS {array of pointers}
Published on
31 December 2024 at 17:06
#c
#vivado
#vivado-hls
1.8k
Views
Sending an array to the IP core through SDK
Published on
30 December 2024 at 08:24
#sdk
#ip
#vivado
1.2k
Views
Ethernet SGMII Interface Design KC705 or KCU105
Published on
04 December 2024 at 16:07
#verilog
#ethernet
#vivado
931
Views
Can I use Vivado block design clock frequencies in my VHDL?
Published on
04 December 2024 at 16:11
#vhdl
#fpga
#vivado
1.1k
Views
Circuit behaves poorly in timing simulation but alright in behavioral - new to verilog
Published on
01 January 2025 at 18:32
#verilog
#fpga
#hdl
#vivado
15.1k
Views
ambiguous clock in event control
Published on
04 December 2024 at 16:03
#verilog
#xilinx
#vivado
4.9k
Views
What is the difference between using a 'constant' and using a number in vhdl
Published on
03 January 2025 at 00:24
#vhdl
#fpga
#synthesis
#vivado
1.9k
Views
Latency and Initiation interval in HLS
Published on
31 December 2024 at 17:03
#xilinx
#vivado
#vivado-hls
40.7k
Views
how to solve 4 bit full adder verilog
Published on
04 December 2024 at 16:00
#xilinx
#vivado
210
Views
To make output LED blink in moore machine
Published on
04 December 2024 at 16:03
#verilog
#vivado
515
Views
Vivado Entirely Eliminating Design During Synthesis - Possibly Constraints Issue
Published on
03 January 2025 at 00:25
#vhdl
#xilinx
#vivado
#synthesis
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