Synthesis on yosys

Question

I have a top file in Verilog and it uses multiple modules instantiated in it that are in different files. If I put all these files in one directory and then I use read Verilog command only on the top file. Will all the files having the modules are be read by this command in the correct order?

Answer 1

If your Verilog files are named after the modules they contain:

read_verilog top.v
hierarchy -top top -libdir .

otherwise, you will have to read in all the modules:

read_verilog *.v
hierarchy -top top