System Verilog: clocking block effects propagation

Question

Consider the following SV code snippet:

module clocks();

  logic a ;
  bit  clk =0;

  initial begin
    forever  #1ns clk = ~clk ;
  end



  clocking cb@(posedge clk);
    default input #1step output negedge;
    output a;
  endclocking

  initial begin
    @(cb);
    #100ps;
    cb.a <= 1 ;
    @(cb);
    #100ps;
    cb.a <= 0 ;
    repeat(10) @(cb);
  end

endmodule

A signal changes after 100ps after the clocking block event through an output synchronous drive. I observe a different behavior while running it with two EDA simulators. With the first simulator, the clocking block output a acts on the second posedge, with the signal changing on the second falling edge. You can see the image below. First simulator

On the other hand, with the second simulator, the clocking block output acts on the FIRST clock, and the effects can be seen on the first falling clock edge. You can see the image below. Second simulator

If, on the other hand, I change the output skew delay, using a delay smaller (es 10ps) than the 100ps delay, the second simulator behaves as the first one ( the a signal changes after the second posedge with the the output skew of 10ps).

Which one of the two simulators is more compliant to the IEEE 1800-2017 SV standard ? In my opinion, according to my comprehension of the standard, the first simulator is more compliant.

The timescale is set to 1fs to avoid any issue related to simulator resolution.

Answer 1

The second simulator (with the unexpected negedge behavior) is VCS. I found the following information on Solvnet:

Enhanced Clocking Block Behavior When Skew is negedge/posedge By default, VCS overrides the clocking event with the skew when the skew is specified as posedge/negedge. However, you can use the -ntb_opts no_cb_edge_override option to avoid overriding the clocking event at input, output, and inout. The following is the behavior of this option at different clocking directions: • Input: Value is sampled at the specified clocking skew delay before the clocking event and the update happens at the clocking event. • Output: The output is updated at the specified clocking skew delay after the clocking event.1

Don't know why VCS has such behavior, but with the flag "-ntb_opts no_cb_edge_override" the simulation runs as in Questa.