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20
Devhide
2025-01-01 18:37:40
2.4k
Views
synopsys dc_shell get_attribute number of digits
Published on
01 January 2025 at 18:37
#tcl
#precision
#synopsys-vcs
15.6k
Views
SystemVerilog: How to connect C function using DPI call in VCS simulator?
Published on
01 January 2025 at 18:40
#c
#system-verilog
#synopsys-vcs
#system-verilog-dpi
485
Views
Synopsys VCS message severity change from error to warning
Published on
01 January 2025 at 18:39
#verilog
#system-verilog
#synopsys-vcs
206
Views
ERROR while coverity scan : No snapshot in stream has analysis summaries
Published on
01 January 2025 at 18:40
#java
#desktop
#coverity
#synopsys-vcs
1.2k
Views
In synopsys VCS, how can I get the raw RTL verilog output file?
Published on
01 January 2025 at 18:39
#verilog
#synopsys-vcs
595
Views
Running a command on multiple files using TCL script
Published on
01 January 2025 at 18:38
#file-io
#tcl
#simulation
#synopsys-vcs
606
Views
What is -quiet in TCL
Published on
01 January 2025 at 18:33
#tcl
#synopsys-vcs
#programming-pearls
3k
Views
Viewing enum names in vcs ucli
Published on
01 January 2025 at 18:34
#enums
#verilog
#system-verilog
#synopsys-vcs
636
Views
low power circuit design in verilog and calculate power for different input sequences
Published on
01 January 2025 at 18:41
#verilog
#system-verilog
#synopsys-vcs
685
Views
SystemVerilog Concurrent Assertion Sequence Dynamic Length
Published on
01 January 2025 at 18:39
#verilog
#system-verilog
#verification
#system-verilog-assertions
#synopsys-vcs
5.1k
Views
How to use Find Scope in Synopsys Verdi
Published on
01 January 2025 at 18:35
#verilog
#synopsys-vcs
4.5k
Views
Synopsys VCS Warning for `define redefined
Published on
01 January 2025 at 18:36
#verilog
#synopsys-vcs
281
Views
TCL processing arguments template, why [set argv {}]
Published on
01 January 2025 at 18:37
#bash
#shell
#tcl
#vivado
#synopsys-vcs
403
Views
System Verilog: clocking block effects propagation
Published on
01 January 2025 at 18:37
#verilog
#system-verilog
#hdl
#questasim
#synopsys-vcs
143
Views
Verilog always vs assign
Published on
01 January 2025 at 18:34
#verilog
#synopsys-vcs
6.2k
Views
why I am not allowed to define unpacked array variable by 8'CC in system verilog?
Published on
01 January 2025 at 18:41
#verilog
#system-verilog
#synopsys-vcs
8.9k
Views
How do I fix "Error-[ICPSD] Invalid combination of drivers"?
Published on
01 January 2025 at 18:38
#verilog
#system-verilog
#hdl
#synopsys-vcs
12k
Views
Get system time in VCS
Published on
01 January 2025 at 18:33
#verilog
#system-verilog
#uvm
#synopsys-vcs
627
Views
Is it possible to fully compile a module and then instantiate it in a testbench separately?
Published on
01 January 2025 at 18:41
#verilog
#system-verilog
#cadence
#questasim
#synopsys-vcs
253
Views
Checking for amount of open files while running SystemVerilog testbench
Published on
01 January 2025 at 18:40
#verilog
#simulation
#system-verilog
#test-bench
#synopsys-vcs
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