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synopsys dc_shell get_attribute number of digits

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#tcl #precision #synopsys-vcs
15.5k
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SystemVerilog: How to connect C function using DPI call in VCS simulator?

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#c #system-verilog #synopsys-vcs #system-verilog-dpi
451
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Synopsys VCS message severity change from error to warning

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#verilog #system-verilog #synopsys-vcs
165
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ERROR while coverity scan : No snapshot in stream has analysis summaries

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#java #desktop #coverity #synopsys-vcs
1.2k
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In synopsys VCS, how can I get the raw RTL verilog output file?

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#verilog #synopsys-vcs
557
Views

Running a command on multiple files using TCL script

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#file-io #tcl #simulation #synopsys-vcs
571
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What is -quiet in TCL

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#tcl #synopsys-vcs #programming-pearls
2.9k
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Viewing enum names in vcs ucli

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#enums #verilog #system-verilog #synopsys-vcs
601
Views

low power circuit design in verilog and calculate power for different input sequences

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#verilog #system-verilog #synopsys-vcs
653
Views

SystemVerilog Concurrent Assertion Sequence Dynamic Length

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#verilog #system-verilog #verification #system-verilog-assertions #synopsys-vcs
5.1k
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How to use Find Scope in Synopsys Verdi

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#verilog #synopsys-vcs
4.5k
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Synopsys VCS Warning for `define redefined

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#verilog #synopsys-vcs
274
Views

TCL processing arguments template, why [set argv {}]

Published on
#bash #shell #tcl #vivado #synopsys-vcs
395
Views

System Verilog: clocking block effects propagation

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#verilog #system-verilog #hdl #questasim #synopsys-vcs
133
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Verilog always vs assign

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#verilog #synopsys-vcs
6.2k
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why I am not allowed to define unpacked array variable by 8'CC in system verilog?

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#verilog #system-verilog #synopsys-vcs
8.9k
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How do I fix "Error-[ICPSD] Invalid combination of drivers"?

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#verilog #system-verilog #hdl #synopsys-vcs
12k
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Get system time in VCS

Published on
#verilog #system-verilog #uvm #synopsys-vcs
621
Views

Is it possible to fully compile a module and then instantiate it in a testbench separately?

Published on
#verilog #system-verilog #cadence #questasim #synopsys-vcs
245
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Checking for amount of open files while running SystemVerilog testbench

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#verilog #simulation #system-verilog #test-bench #synopsys-vcs

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