The first parameter transfer I wrote generated the code I wanted spinalHDL CODE
io.data := SpinalMap(io.funct3, B"3'b0" -> B"2'b1",
B"3'b1" -> B"2'b10",
B"3'b10" -> B"2'b11",
B"3'b11" -> B"2'b00",
default -> B"2'b00")
generate verilog code
always @(*) begin
case(io_funct3)
3'b000 : begin
_zz_io_data = 2'b01;
end
3'b001 : begin
_zz_io_data = 2'b10;
end
3'b010 : begin
_zz_io_data = 2'b11;
end
3'b011 : begin
_zz_io_data = 2'b00;
end
default : begin
_zz_io_data = 2'b00;
end
endcase
end
The second parameter transfer I wrote generated the code
spinalHDL CODE
val table:Seq[(Any, Bits)] = Seq(B"3'b0" -> B"2'b1", B"3'b1" -> B"2'b10", B"3'b10" -> B"2'b11", B"3'b11" -> B"2'b00", spinal.core.default -> B"2'b00")
io.data := SpinalMap.list(io.funct3, table)
verilog code
always @(*) begin
if((io_funct3 == table_0_0)) begin
_zz_io_data = table_0_1;
end else if((io_funct3 == table_1_0)) begin
_zz_io_data = table_1_1;
end else if((io_funct3 == table_2_0)) begin
_zz_io_data = table_2_1;
end else if((io_funct3 == table_3_0)) begin
_zz_io_data = table_3_1;
end else begin
_zz_io_data = table_4_1;
end
end
How do I use the second type of spinalHDL code to generate the first type of verilog code?Why do the two writing methods generate different verilog code?
It seems that I only generate case statements by directly passing (Any, T) * types, and I generate if statements using other set types