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List Question
14
Devhide
2024-12-26 13:19:11
401
Views
Strange behaviour of yosys on FSM while building for iCE40
Published on
26 December 2024 at 13:19
#verilog
#yosys
#spinalhdl
229
Views
How to connect a Flow to a Stream in SpinalHDL
Published on
26 December 2024 at 13:11
#hdl
#spinalhdl
53
Views
scala process never finishes in IDEA
Published on
26 December 2024 at 13:07
#java
#scala
#intellij-idea
#jvm
#spinalhdl
48
Views
What is the meaning of Masked() in Scala's library SpinalHDL
Published on
28 December 2024 at 11:08
#spinalhdl
139
Views
Vexriscv - implement ram as block ram
Published on
26 December 2024 at 13:05
#block
#fpga
#ram
#riscv
#spinalhdl
87
Views
Is it possible to convert from Bits to SpinalEnum?
Published on
05 January 2025 at 09:41
#spinalhdl
180
Views
SpinalHDL ConfigClockDomain not work, how to drive configured clock domain when simulating?
Published on
26 December 2024 at 13:28
#java
#scala
#spinalhdl
66
Views
Can I use SpinalEnum as field in RegIf?
Published on
26 December 2024 at 13:03
#spinalhdl
317
Views
Connecting AXI Stream to StreamFifo
Published on
26 December 2024 at 13:05
#scala
#spinalhdl
316
Views
How to write nested fsm in Chisel like SpinalHDL does?
Published on
26 December 2024 at 13:16
#chisel
#spinalhdl
74
Views
combine logical expression for StaticMemeoryTranslatorPlugin used in VexRiscv
Published on
26 December 2024 at 13:25
#scala
#spinalhdl
61
Views
The SpinalMap parameter type passed in Spinalhdl is different, resulting in meaningless generated code
Published on
26 December 2024 at 13:29
#hdl
#spinalhdl
94
Views
Giving User-Defined properties for a signal
Published on
26 December 2024 at 13:09
#spinalhdl
134
Views
How can I make a ternary condition in SpinalHDL?
Published on
26 December 2024 at 13:12
#fpga
#spinalhdl
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