Unable to synthesize a signal because of bad synchronous descriptionin VHDL

Question

I have a problem with the Synthesise in VHDL. This is the part of the code where it gives me error:

CASE stare_curenta IS
        WHEN verde =>
            stare_urm <= albastru;

                rosuS1368stg <= '1';
                galbenS1368stg <= '0';
                verdeS1368stg <= '0';

                rosuS1368 <= '0';
                galbenS1368 <= '0';
                if ( clock'event and clock = '0') then
                    galbenS1368 <= '1';
                end if;
                verdeS1368 <= '1';

                rosup1v1i4v2i3v1i2v2i6v1i5v2i8v1i7v2 <= '0';
                verdep1v1i4v2i3v1i2v2i6v1i5v2i8v1i7v2 <= '1';

                rosuS2457stg <= '1';
                galbenS2457stg <= '0';
                if (clock'event and clock = '0') then
                    galbenS2457stg <= '1';
                end if;
                verdeS2457stg <= '0';

                rosuS2457 <= '1';
                galbenS2457 <= '0';
                verdeS2457 <= '0';

                rosup2v1i1v2i4v1i3v2i5v1i8v2i7v1i6v2 <= '1';
                verdep2v1i1v2i4v1i3v2i5v1i8v2i7v1i6v2 <= '0';

I have another process of clock and clock'event below, like this one:

PROCESS(clock,stare_urm)
        BEGIN
            if (clock'event and clock = '1')then
                stare_curenta <= stare_urm;
            end if;
    END PROCESS;

The 'Check Syntax' and 'Simulation' are going well, only the Synthesise it gives me the error: Signal galbenS1368 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Thank you!

Answer 1

The problem is:

if (clock'event and clock = '0') then

inside your state decoding. It's not a syntax problem, and simulators will dutifully carry out exactly what you wrote (though you may not get the results you intended), but as the error message says, it's not a supported synthesis style (embedding a clocked segment of code, i.e. a portion of a process intended to create a register, inside a larger combinational process).

Either way, I'm not sure it's what you really want to do. A process is evaluated when a signal in its sensitivity list changes. The way you've coded it, you're effectively saying "when this process is evaluated, if at that exact instant the clock is falling, register the signal", even though what you probably intended was to assign a value which is then registered on the next falling clock edge.

Assuming that last statement is so, it basically tells you how to code it. It has two parts. (1) assign a value:

when verde =>
  ...
  galbenS2457stg <= '1';

(2) which is registered on the next falling clock edge:

process (clock)
begin
  if clock'event and clock = '0' then
    galbenS2457stg_reg <= galbenS2457stg;
  end if;
end process;

Synchronous design in synthesis is essentially register -> a bunch of combinational logic -> register -> combinational logic -> etc. Coding it like that, with your registers separated from your combinational logic in code, is a good way to start thinking more in terms of hardware.

edit for clarification

Based on your responses in the comments, it seems I was not clear enough on what I was recommending.

You have some sort of process to handle your state machine. I'm assuming most of it is unclocked. You tried to insert small, clocked portions into it, and this is what the tool is complaining about. I'm suggesting you try coding in the following manner (not complete code, just to illustrate the point):

comb1 : process (...) -- fill in sensitivity list as needed
begin
  -- state machine decode
  ...
    when verde =>
      ...
      galbenS2457stg <= '1';
  ...
end process comb1;

clocked1 : process (clock)
begin
  if clock'event and clock = '0' then
    galbenS2457stg_reg <= galbenS2457stg;
  end if;
end process clocked1;

Change the names if you need to - since you only posted part of your code, it wasn't evident that galbenS2457stg was an output at all. However you name them, the signal assigned in your state decode process should be an internal signal, and would be declared in the architecture declarative region, not as an output port, while the clocked signal would be the output port, and would be declared as such.