Unexpected behaviour in tristate switch VHDL

Question

I have discovered an unexpected problem with a tristate driver developed in VHDL. The behavior of the tristate driver is not understandable in the simulation.

Please have a look at the following code snippet where the signal line_en is set:

process(all)
begin
if (reset = '0') then
    line_en <= '0';
elsif (A /= A_reg) then
    line_en <= '0';
elsif (B_reg /= B) then
    line_en <= '1';
else
    line_en <= line_en;
end if;
end process;

In the simulation it happens now that signal B_reg and B both jump from "0000" to "ZZZZ" at the same time. However, in the transition from "0000" to "ZZZZ" line_en goes to '1' although this should not happen with (B_reg /= B), so the condition must not become true in my opinion.

Attached below a screenshot of the simulation:

It is for simulation purposes only. Synthesization is not yet desired.

Thanks in advance for any hint where I made a mistake that I can't see myself at the moment. Maybe it's a timing problem because the process itself is not clocked, so it runs asynchronously.

Answer 1

The comments are right and seemingly pointing in the right direction. It is caused from delta delay (i.e. simulation steps) when simulation is running. By reconsideration of the above logic design and how Vivado integrated simulator works, I came to the conclusion that creating an asynchronous logic can cause flaws or behavior that is not desired or deviates from a synthesized design.

It is for simulation purposes only. I'm aware that comparison with Z won't work in synthesized logic. I added this to the opening question.