I want to create a IPC communication stack between the 2 processor cores of imx8mm viz A53 and M4 and I don't want to use interrupts. I have two types of messages to be shared between the cores, One is cyclic data that is read every 10ms, so it is just a simple struct placed in shared memory which is written by m4 and read by a53.
My question is regarding another msg type which is Acyclic data, so it is not a fixed struct, it is some type of packet which can be max 128 bytes in size, I will also append some header, footer, datalen, msg Id, to it bringing the total size to let's say 136 byte (word aligned)
My idea is to define a queue,
struct packet
{
uint8 Packet[136];
}
struct Queue
{
u32 Read;
u32 Write;
Packet Msg[10];
}
and i will place the queue object in shared memory Queue M4toA53QHandle @ "SM_segment"
read and write are 32 bit, so that read and write are atomic. Also no element in the queue is written by both cores. A53 will only modify read index and m4 will only modify write and Packet data.
My question is little on the broader range, do you see any concurreny or sequencing issue with this approach? I read about out of order memory operations, which might cause my write index to update before packet is fully copied to queue slot, but 'DMB' will solve that issue.
For any given share memory location, as long as one side always read and one side always write, then it should work provided that you update the message content before update the "available to read" index/pointer.