Verilog always vs assign

Question

Is it legal for a simulator to evaluate clk_out1 in the next active Verilog scheduling window w.r.t clk? clk_out2 seems to be updated in the same scheduling window as clk.

reg clk_out1;
always @(*)
    clk_out1 = clk;

assign clk_out2 = clk;

In this image Red - NBA region Yellow - Active region

Answer 1

The Verilog scheduling semantics dictate that both assignments happen in the same active scheduling region. They will behave as if clk, clk_out1 and clk_out2 are aliases for each other. This is assuming you used a regular blocking assignment and not a non-blocking assignment to clk_out1, which is the recommended way of assigning clocks in RTL.