VHDL - Behavioral work correctly, Post Route has problem

Question

I'm new on StackOverflow and I'm sorry for eventual error.
I'm workin on VHDL and I have a problem with the Post-Place & Route. While behavioral works correctly, Post-Place & Route has problem and the result remain UNDEFINED for the all the time.

entity step1 is
  port (   d: in std_logic_vector (0 to 5);
        clk : in std_logic;
            RESET: in std_logic;
        q: out std_logic_vector (0 to 5)
         );
end step1;

architecture Behavioral of step1 is

begin
  ff: process (clk)
  begin
      if (clk'event and clk='1') then
        if (RESET = '1') then
          q <= "000000";
          else
          q <= d;
          end if;
    end if;
    end process;
end Behavioral;

I place here the code. It should be a flip flop D that I use to make a pipeline architecture.
Thanks for your reply, and please excuse me for any mistake.
Here's the test bench:

entity test_step1 is
end test_step1
ARCHITECTURE behavior OF test_step1 IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT step1
PORT(
     input : IN  std_logic_vector(0 to 5);
     clk : IN  std_logic;
     RESET : IN  std_logic;
     output : OUT  std_logic_vector(0 to 5)
    );
END COMPONENT;
--Inputs
signal input : std_logic_vector(0 to 5) := (others => '0');
signal clk : std_logic := '0';
signal RESET : std_logic := '0';

--Outputs
signal output : std_logic_vector(0 to 5);

-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: step1 PORT MAP (
      input => input,
      clk => clk,
      RESET => RESET,
      output => output
    );

 -- Clock process definitions
 clk_process :process
 begin
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
 end process;
 -- Stimulus process
 stim_proc: process 
 begin    
    -- hold reset state for 100 ns.
  RESET <= '1';
    wait for 10 ns;
  RESET <= '0';
  input <= "111111";
    wait for clk_period*10;
  input <= "101010";

  -- insert stimulus here 

  wait;
  end process;

 END;

Answer 1

The first warning messages for HDL Compiler 89 and 648 found on the internet are:

WARNING:HDLCompiler:89 - "my_module" remains a black-box since it has no binding entity.

WARNING:Simulator:648 - "Top_LCD_test.vhd" Line 35. Instance top_lcd is unboundCompiling architecture behavior of entity testbench

This means that the compiler has not fount any entity corresponding to the component used in your testbench.

In your case, the port names of your entity and component didn't match !

Try to use the same names in port for the component and entity :

entity test_step1 is
end test_step1;
ARCHITECTURE behavior OF test_step1 IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT step1
PORT(
     d : IN  std_logic_vector(0 to 5);
     clk : IN  std_logic;
     RESET : IN  std_logic;
     q : OUT  std_logic_vector(0 to 5)
    );
END COMPONENT;
--Inputs
signal input : std_logic_vector(0 to 5) := (others => '0');
signal clk : std_logic := '0';
signal RESET : std_logic := '0';

--Outputs
signal output : std_logic_vector(0 to 5);

-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: step1 PORT MAP (
      d => input,
      clk => clk,
      RESET => RESET,
      q => output
    );

 -- Clock process definitions
 clk_process :process
 begin
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
 end process;
 -- Stimulus process
 stim_proc: process 
 begin    
    -- hold reset state for 100 ns.
  RESET <= '1';
    wait for 10 ns;
  RESET <= '0';
  input <= "111111";
    wait for clk_period*10;
  input <= "101010";

  -- insert stimulus here 

  wait;
  end process;