VHDL OR logic with 32 bit vector

Question

zero <= result_i(31) OR result_i(30) OR result_i(29) OR result_i(28)
        OR result_i(27) OR result_i(26) OR result_i(25) OR result_i(24)
        OR result_i(23) OR result_i(22) OR result_i(21) OR result_i(20)
        OR result_i(19) OR result_i(18) OR result_i(17) OR result_i(16)
        OR result_i(15) OR result_i(14) OR result_i(13) OR result_i(12)
        OR result_i(11) OR result_i(10) OR result_i(9) OR result_i(8)
        OR result_i(7) OR result_i(6) OR result_i(5) OR result_i(4)
        OR result_i(3) OR result_i(2) OR result_i(1) OR result_i(0);

How can I make this shorter?

Answer 1

I am assuming you are using std_logic/std_logic_vector types. Then you can use or_reduce from ieee.std_logic_misc.

library ieee;
use ieee.std_logic_misc.or_reduce;
...
zero <= or_reduce(result_i);

Or write your own function:

function or_reduce(vector : std_logic_vector) return std_logic is
    variable result : std_logic := '0';
begin
    for i in vector'range loop
        result := result or vector(i);
    end loop
    return result;
end function;

A general tip if you are just starting out with VHDL is to not forget about functions and procedures. Unlike Verilog (Without SystemVerilog) VHDL has good support for writing clean and high level code, even for synthesis, using functions and procedures. If you are doing something repetitive it is a sure sign that it should be wrapped in a function/procedure. In this case there already was a standard function ready to be used though.

You might also want to consider pipelining the or-reduction and inserting flip-flops between the stages. Maybe the 32-bit reduction that you use in your example should still run a reasonably high frequency in an FPGA device but if you are going to use more bits or target a really high frequency you might want to use an or-tree where no more than 6-8 bits are or:ed in each pipeline stage. You can still re-use the or_reduce function for the intermediate operations though.

Answer 2

You can achieve it with vhdl revision 2008

VHDL-2008 defines unary operators, like these:

outp <= and "11011";

outp <= xor "11011";

So in your case it would be:

zero <= or result_i;