What are phy page (physical layer/phy register) as in "phy_write_paged" function

Question

I am reading RTL_ReakTek driver code for NIC driver r8169 and it does some phy registers writing/phy config register writing/ with functions like these

pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);// It must be for phy config register write/ But what is phy_write_paged/

are there any memory pages? in physical layer handling by Operating system, if yes please tell me is it same as the concept of kernel pages for virtual memory mapping into kernel memory. I assumes driver need to do with

MMIO registers

Phy registers

Phy Config registers

PHY Paged memory represention

For handling devices

Please explain what all these above are? and how they are handled.

Answer 1

PHY registers are accessed via packets on a serial management bus known as MDIO, SMI or MIIM, depending on who you ask. The original packet format on this bus as defined by Clause 22 of IEEE 803.3 supports access to up to 32 registers on 32 different PHY addresses. The first 16 registers are defined by IEEE 802.3 and the remaining 16 are defined by the PHY vendor.

If the PHY supported more than 32 registers, the vendor could define one of the vendor-specified registers as a "page select" register to select different banks of 32 vendor-specified registers. That is what the phy_read_paged and phy_write_paged functions do. They select the page, read or write the register, and restore the original page, all while holding a lock on the bus to prevent interference from other code that is trying to access the registers.

A later revision of IEEE 802.3 defined an optional extension of the MDIO packet format in Clause 45 that allowed each of the 32 PHY addresses to support up to 32 device addresses (the different addresses are for different, defined uses) with up to 65536 "MMD" registers for each device address. An even later revision defined registers 13 and 14 of the original Clause 22 registers to be used to access the MMD registers indirectly. The phy_read_mmd and phy_write_mmd functions are for accessing these MMD registers (if supported). Some PHY chips may support Clause 45 directly, others may use Clause 22 registers 13 and 14 to access the MMD registers, others may have some custom way to access the MMD registers, and others might not support the MMD registers at all. The phy_read_mmd and phy_write_mmd take care of the differences in methods for accessing the MMD registers.