What do the %envregN special registers hold?

Question

I've read: CUDA PTX code %envreg<32> special registers . The poster there was satisfied with not trying to treat OpenCL-originating PTX as a regular CUDA PTX. But - their question about %envN registers was not properly answered.

Mark Harris wrote that

OpenCL supports larger grids than most NVIDIA GPUs support, so grid sizes need to be virtualized by dividing across multiple actual grid launches, and so offsets are necessary. Also in OpenCL, indices do not necessarily start from (0, 0, 0), the user can specify offsets which the driver must pass to the kernel. Therefore the registers initialized for OpenCL and CUDA C launches are different.

So, do the %envN registers make up the "virtual grid index"? And what does each of these registers hold?

Answer 1

The extent of the answer that can be authoritatively given is what is in the PTX documentation:

A set of 32 pre-defined read-only registers used to capture execution environment of PTX program outside of PTX virtual machine. These registers are initialized by the driver prior to kernel launch and can contain cta-wide or grid-wide values.

Anything beyond that would have to be:

1. discovered via reverse engineering or disclosed by someone with authoritative/unpublished knowledge
2. subject to change (being undocumented)
3. evidently under control of the driver, which means that for a different driver (e.g. CUDA vs. OpenCL) the contents and/or interpretation might be different.

If you think that NVIDIA documentation should be improved in any way, my suggestion would be to file a bug.