What is odd-even register pairing in Sparc processor?

Question

A Sparc simulator that I have gave me Trap: illegal_instruction, Destination is an odd-even register pair for an ld instruction.

What exactly is the odd-even pairing in the processor? Does it have something to do with memory alignment? I have gone through the manual but it wasn't explained in detail.

Answer 1

I'm not absolutely sure, but the error message might refer to an ldd instruction:

The ldd instruction loads two registers at once: The even register (e.g. i2) specified and the following odd register (e.g. i3).

According to the Sparc v8 manual, there may be two different behaviors if you specify an odd register (such as i3) depending on the actual CPU used:

• Some CPUs will cause an exception (this is what seems to happen in your case)
• Other CPUs ignore the low bit of the register number and interpret i3 as i2 (because i3 would be loaded anyway, this also makes sense)