what is the difference between synthesis and simulation (VHDL)

Question

Im am working on a VHDL project that includes an fsm. Some states change according to a counter. It dit not work until i put 'clk' in the sensitivity list, besides the current state and the input. I know that during synthesis, the sensitivity not used, or discarded. But how can that have such an impact on the result in the simulation? if a leave this 'clk', would the fsm perform as i want op an FPGA?

thanks,

David

Answer 1

This is the simple explanation:

The simulator uses the sensitivity list to figure out when it needs to run the process. The reason why the simulator needs hints to figure out when to run the process is because computer processors can only do one (or only a few in multicore systems) thing at a time and the processor will have to take turns running each part of your design. The sensitivity list allows simulation to run in a reasonable time frame.

When you synthesize code into an ASIC or FPGA, the process is always "running" since it has dedicated hardware.

When you simulate a state machine without the clock in the sensitivity list, the process will never run on the clock edges, but only on changes to your input. If you have the state transition implemented as a flip flop (if clk'event and clk = '1') then your state transition will never be simulated unless you happen to change your input at the same time as the clock's rising edge. You should probably leave the clock in the sensitivity list, assuming the FSM changes on clock edges.

Also, try to proofread your questions.

Answer 2

Synthesis tools focus on logic design (FPGA, ASIC) and ignore sensitivity lists because there are only three basic types of logic: Combinational logic, edge sensitive storage (flip-flops and some RAM), and level sensitive storage (latches and some RAM).

Combinational logic requires all input signals to be on the sensitivity list. From a synthesis tool perspective, if one is missing, they can either ignore the sensitivity list and treat it as if all inputs were on the sensitivity list, or produce some complicated combination of flip-flops and combinational logic that probably will not do what the user wanted anyway. Both of these have an implementation cost to the vendor, hence, why invest money (development time) to create something that is not useful. As a result, the only good investment is to simplify and ignore the sensitivity list.

Simulators on the other hand, have a bigger perspective than just logic design. The language defines sensitivity lists as to indicate when the code should run. So simulators implement that semantic with a high fidelity.

Long term it may make you happy to know that VHDL-2008 allows the keyword "all" to be used in a sensitivity list to replace the signal inputs there. This is intended to simplify the modeling of combinational logic. Syntax is as follows:

MyStateMachine : process(all) 
begin
  -- my statemachine logic 
end process MyStateMachine ; 

Turn on the VHDL-2008 switch and it out in your synthesis tool. If it does not work, be sure to submit a bug against the tool.