What is the implication of not resetting a register in reset aware always_ff block?

Question

What is the consequence of not resetting a flop inside a reset aware alaways_ff block?

Example 1:

always_ff @(posedge clk, negedge rst) begin
   if (~rst) begin
      reg_a <='0;
      reg_b <='0;
   end else begin
      if (condition_1) begin
         reg_a <= some_signal;
      end else if (condition_2) begin
         reg_b <= some signal;
      end
   end
end

Example 2:

always_ff @(posedge clk, negedge rst) begin
   if (~rst) begin
      reg_a <='0;
   end else begin
      if (condition_1) begin
         reg_a <= some_signal;
      end else if (condition_2) begin
         reg_b <= some signal;
      end
   end
end

The only difference between example 1 and 2 is, in example 2, reg_b doesn't have any reset condition. What will be the consequence of this mistake in backend/synthesis? I've front end RTL design background with little experience in sylthesis. So, I'm trying to understand why example 2 above is a bad practice.

One obvious problem is- just after reset reg_b will be X in example 2. So if reg_b is used in any control logic then it might introduce bug in design. Other than this what other problem this can create?

Answer 1

I do not think that it would cause any error during synthesis or PnR.
On huge designs I did encountered some ff that were not reseted. It can avoid some unnecessary constraints on the PnR tools.
As you said however, you should be careful not to introduce bugs by using it before it was written as it will be 'X' until then.