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Divide by 2 clock and corresponding reset generation

Published on
#verilog #reset #clock #synthesis #asic
4.2k
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Using an ASIC to brute force MD5

Published on
#hash #md5 #brute-force #asic
1.7k
Views

OpenCL (or Other) Programming for ASIC devices?

Published on
#c++ #c #opencl #asic
1.1k
Views

Store std_logic bits in ascending order into a large array

Published on
#vhdl #verilog #fpga #synthesis #asic
319
Views

Using firmware on ASIC simulation environment

Published on
#verification #firmware #asic
3.1k
Views

Asynchronous FIFO depth calculation

Published on
#fpga #asic #soc #digital-design
398
Views

relationship between flopping and meta-stability

Published on
#fpga #asic
889
Views

Image-processing ASIC

Published on
#image-processing #computer-vision #asic
3.4k
Views

Why is the following clock multiplication Verilog code not working for me?

Published on
#verilog #system-verilog #asic #soc
326
Views

Difference between process and "vanilla" VHDL

Published on
#vhdl #fpga #hardware #asic
628
Views

Is it possible to display coverage of a specific bin within a coverpoint in a logfile using the simvision tool?

Published on
#system-verilog #hdl #asic
1.1k
Views

What is maximum size of the Queue in SystemVerilog?

Published on
#system-verilog #verification #asic
508
Views

SystemVerilog : Port connection based on parameter

Published on
#verilog #system-verilog #hdl #asic
720
Views

What is the implication of not resetting a register in reset aware always_ff block?

Published on
#system-verilog #register-transfer-level #asic
468
Views

ASIC design - combinational logic

Published on
#asic
225
Views

Adding skew to improve timing

Published on
#verilog #fpga #system-verilog #register-transfer-level #asic
637
Views

Synopsys design compiler- view datapath extraction results

Published on
#vhdl #synthesis #asic
353
Views

Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?

Published on
#verilog #fpga #hdl #register-transfer-level #asic
106
Views

Propagational delay in circuits

Published on
#circuit #vlsi #asic
251
Views

how to track errors in FPGA/ASIC development using post place'n' route and/or post synthesis simulation?

Published on
#simulation #fpga #synthesis #asic

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