I've noticed that some versions of the Intel PMU include a counter like PARTIAL_RAT_STALLS.SCOREBOARD on Cascade Lake that is documented as "This event counts cycles during which the microcode scoreboard stalls happen." I can't find any information online as to what the microcode scoreboard is. There's a similar counter in Ice Lake: RESOURCE_STALLS.SCOREBOARD documented as "Counts cycles where the pipeline is stalled due to serializing operations."
Both counters are used under Top-down Microarchitecture Analysis as the level 4 counter Serializing_Operation documented as "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance."
I have seen this counter increment for other instructions that I wouldn't consider serializing such as rdtsc (of course rdtscp is serializing). I've seen it increment in a few other strange places as well but I don't have an easy way to measure where precisely.