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20
Devhide
2025-01-06 15:31:21
339
Views
Can we measure successful store-forwarding with Intel's performance counters?
Published on
06 January 2025 at 15:31
#performance
#x86
#intel-pmu
1.5k
Views
How to use rdpmc instruction for counting L1d cache miss?
Published on
06 January 2025 at 15:29
#assembly
#x86
#perf
#intel-pmu
97
Views
How to count offcore PMU events on an old kernel?
Published on
06 January 2025 at 15:27
#profiling
#perf
#intel-pmu
50
Views
How to count the number of data loaded into the cache but not used?
Published on
06 January 2025 at 15:30
#caching
#x86
#perf
#cpu-cache
#intel-pmu
69
Views
Why does it need to be divided by 9 when calculating UPI bandwidth on the Intel platform using UNC_UPI_TxL_FLITS.ALL_DATA event?
Published on
06 January 2025 at 15:41
#x86
#cpu-architecture
#intel
#perf
#intel-pmu
2.6k
Views
Intel Performance Monitor -- any way to monitor per-process?
Published on
06 January 2025 at 15:29
#c
#performance
#winapi
#performancecounter
#intel-pmu
414
Views
How to use rdpmc instruction on AMD (EPYC) processor?
Published on
06 January 2025 at 15:28
#linux
#performance
#x86
#amd-processor
#intel-pmu
154
Views
`SIGSEGV` when reading `HW_CPU_CYCLES` on Alder Lake efficiency cores
Published on
06 January 2025 at 15:30
#linux
#x86
#performancecounter
#perf
#intel-pmu
351
Views
cpuid: reported micro-architecture seems ambiguous
Published on
06 January 2025 at 15:27
#intel
#cpu-architecture
#cpuid
#intel-pmu
359
Views
Read PMU counters using wrmsrl and rdmsrl
Published on
06 January 2025 at 15:26
#c
#linux-kernel
#kernel-module
#intel-pmu
#msr
637
Views
Performance Counters and IMC Counter Not Matching
Published on
06 January 2025 at 15:27
#linux-kernel
#performancecounter
#perf
#memory-access
#intel-pmu
1.1k
Views
Using the perf events from perf list programatically
Published on
06 January 2025 at 15:28
#linux
#performance
#perf
#intel-pmu
877
Views
Why "setne %al" used "a lot of cycles" in perf annotation?
Published on
06 January 2025 at 15:28
#assembly
#x86
#intel
#perf
#intel-pmu
421
Views
Why does the number of uops per iteration increase with the stride of streaming loads?
Published on
06 January 2025 at 15:31
#assembly
#x86
#cpu-architecture
#intel-pmu
945
Views
What causes the DTLB_LOAD_MISSES.WALK_* performance events to occur?
Published on
06 January 2025 at 15:30
#x86
#cpu-architecture
#tlb
#intel-pmu
831
Views
On Skylake (SKL) why are there L2 writebacks in a read-only workload that exceeds the L3 size?
Published on
06 January 2025 at 15:32
#performance
#x86
#cpu-cache
#perf
#intel-pmu
492
Views
Is it possible for the RESOURCE_STALLS.RS event to occur even when the RS is not completely full?
Published on
06 January 2025 at 15:32
#performance
#x86
#intel
#cpu-architecture
#intel-pmu
272
Views
Vtune: Accuracy of Intel sampling drivers when vtune measurement run on a machine running other tasks
Published on
06 January 2025 at 15:32
#linux
#performance
#intel
#intel-vtune
#intel-pmu
532
Views
how to reset general purpose performance counter of intel
Published on
06 January 2025 at 15:29
#performance
#assembly
#x86
#msr
#intel-pmu
115
Views
What does this sentence mean in the context of perf tool: "Supports address when precise (Precise event)"?
Published on
06 January 2025 at 15:32
#linux
#profiling
#perf
#memory-profiling
#intel-pmu
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