Question

Can we measure successful store-forwarding with Intel's performance counters?

score 298 · Answer 1 · 2017-09-09 22:54:15

298

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Can we measure successful store-forwarding with Intel's performance counters?

Published on 09 September 2017 at 22:54

score 1.5k · Answer 2 · 2020-10-05 14:28:55

1.5k

Views

How to use rdpmc instruction for counting L1d cache miss?

Published on 05 October 2020 at 14:28

score 55 · Answer 3 · 2023-10-17 03:55:07

55

Views

How to count offcore PMU events on an old kernel?

Published on 17 October 2023 at 03:55

score 22 · Answer 4 · 2023-11-06 13:59:18

22

Views

How to count the number of data loaded into the cache but not used?

Published on 06 November 2023 at 13:59

score 26 · Answer 5 · 2023-12-22 08:34:17

26

Views

Why does it need to be divided by 9 when calculating UPI bandwidth on the Intel platform using UNC_UPI_TxL_FLITS.ALL_DATA event?

Published on 22 December 2023 at 08:34

score 2.5k · Answer 6 · 2012-05-17 23:41:22

2.5k

Views

Intel Performance Monitor -- any way to monitor per-process?

Published on 17 May 2012 at 23:41

score 375 · Answer 7 · 2022-04-28 14:47:37

375

Views

How to use rdpmc instruction on AMD (EPYC) processor?

Published on 28 April 2022 at 14:47

score 112 · Answer 8 · 2022-04-28 06:20:30

112

Views

`SIGSEGV` when reading `HW_CPU_CYCLES` on Alder Lake efficiency cores

Published on 28 April 2022 at 06:20

score 300 · Answer 9 · 2022-05-03 21:45:15

300

Views

cpuid: reported micro-architecture seems ambiguous

Published on 03 May 2022 at 21:45

score 319 · Answer 10 · 2022-05-09 20:01:20

319

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Read PMU counters using wrmsrl and rdmsrl

Published on 09 May 2022 at 20:01

score 624 · Answer 11 · 2021-05-13 03:43:42

624

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Performance Counters and IMC Counter Not Matching

Published on 13 May 2021 at 03:43

score 1.1k · Answer 12 · 2020-08-30 02:24:53

1.1k

Views

Using the perf events from perf list programatically

Published on 30 August 2020 at 02:24

score 865 · Answer 13 · 2020-09-08 08:02:12

865

Views

Why "setne %al" used "a lot of cycles" in perf annotation?

Published on 08 September 2020 at 08:02

score 407 · Answer 14 · 2018-09-26 23:25:07

407

Views

Why does the number of uops per iteration increase with the stride of streaming loads?

Published on 26 September 2018 at 23:25

score 931 · Answer 15 · 2018-09-29 22:05:13

931

Views

What causes the DTLB_LOAD_MISSES.WALK_* performance events to occur?

Published on 29 September 2018 at 22:05

score 821 · Answer 16 · 2018-09-29 05:09:30

821

Views

On Skylake (SKL) why are there L2 writebacks in a read-only workload that exceeds the L3 size?

Published on 29 September 2018 at 05:09

score 480 · Answer 17 · 2018-10-05 00:15:37

480

Views

Is it possible for the RESOURCE_STALLS.RS event to occur even when the RS is not completely full?

Published on 05 October 2018 at 00:15

score 260 · Answer 18 · 2021-06-06 07:40:12

260

Views

Vtune: Accuracy of Intel sampling drivers when vtune measurement run on a machine running other tasks

Published on 06 June 2021 at 07:40

score 518 · Answer 19 · 2014-01-29 00:48:15

518

Views

how to reset general purpose performance counter of intel

Published on 29 January 2014 at 00:48

score 105 · Answer 20 · 2022-03-26 14:39:55

105

Views

What does this sentence mean in the context of perf tool: "Supports address when precise (Precise event)"?

Published on 26 March 2022 at 14:39

List Question

Can we measure successful store-forwarding with Intel's performance counters?

How to use rdpmc instruction for counting L1d cache miss?

How to count offcore PMU events on an old kernel?

How to count the number of data loaded into the cache but not used?

Why does it need to be divided by 9 when calculating UPI bandwidth on the Intel platform using UNC_UPI_TxL_FLITS.ALL_DATA event?

Intel Performance Monitor -- any way to monitor per-process?

How to use rdpmc instruction on AMD (EPYC) processor?

`SIGSEGV` when reading `HW_CPU_CYCLES` on Alder Lake efficiency cores

cpuid: reported micro-architecture seems ambiguous

Read PMU counters using wrmsrl and rdmsrl

Performance Counters and IMC Counter Not Matching

Using the perf events from perf list programatically

Why "setne %al" used "a lot of cycles" in perf annotation?

Why does the number of uops per iteration increase with the stride of streaming loads?

What causes the DTLB_LOAD_MISSES.WALK_* performance events to occur?

On Skylake (SKL) why are there L2 writebacks in a read-only workload that exceeds the L3 size?

Is it possible for the RESOURCE_STALLS.RS event to occur even when the RS is not completely full?

Vtune: Accuracy of Intel sampling drivers when vtune measurement run on a machine running other tasks

how to reset general purpose performance counter of intel

What does this sentence mean in the context of perf tool: "Supports address when precise (Precise event)"?

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