why I am not allowed to define unpacked array variable by 8'CC in system verilog?

Question

I have tried with the below code:

module try;
int a[8];
initial
begin
a = 8'hCC;
$display(a);
end
endmodule

This is giving error as:

Incompatible complex type assignment
  Type of source expression is incompatible with type of target expression. 
  Mismatching types cannot be used in assignments, initializations and 
  instantiations. The type of the target is 'bit$[0:7]', while the type of the
  source is 'bit[7:0]'.

Answer 1

At least in your code, you cannot assign the array a to have value 8'hCC as a is an int array (int a[8]) but even if you were to define a as bit a[8] or logic a[8], you would still be unable to do the kind of assignment you are trying to do. Verilog as two types of "arrays" (though I like to call packed arrays "vectors" and unpacked arrays "arrays" for clarity). More about the difference between the two can be found here:

packed vs unpacked vectors in system verilog

In short, the internal representation of an unpacked array guarantees nothing about the relationship of array elements, ie that each element is separate and the spacing between elements in memory is implementation dependent. Thus, trying to assign two adjacent element with a statement like a = 8'hCC is illegal and not defined (even if a is of type bit, the second 0 in 8'hCC might go to a[1] or somewhere between a[0] and a[1]). This is why packed arrays exist. Unpacked arrays have their place, typically in testbenches or defining a bunch of repeating signals that are disjoint; but you should use packed arrays for the type of assignment you are trying to do (which DO guarantee adjacency); so you bit [7:0] a instead.