Below is Data transfer instruction format for 32-bit ARM and MIPS architecture. 32-bit ARM architecture have 4 bit opcode because there are 16 registers (2^4=16).32-bit MIPS architecture have 6 bit opcode. Should not it be 5 bits considering there are 32 registers in MIPS?
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Opcode encoding and register field encoding and immediate/const encoding are different, with different trade offs among them, as making one larger makes the others smaller, when they have to co-exist in the same instruction.
The size of each field determines the number of different items that can be represented in that field.
In comparison with MIPS, for example, RISC V, shortens the "const" immediate field in I-type instructions to 12 bits, which allows for larger opcode fields — 7 bits in the base instruction set opcode field, plus 3 extra bits in func (the fields are also generally reversed, going right to left):
+-------------------------------------------+
| imm:12 | rs1:5 | func:3 | rd:5 | opcode:7 | I-Type
+-------------------------------------------+
These extra opcode bits are used to:
The number of registers has nothing to do with the number of opcode bits, it's related to the number of supported instructions (which still isn't a hard limiting factor, considering techniques like instruction prefixes exist).
On the other hand, the operand bit count (Rs and Rd in your picture) are related to the number of registers (they are 5 bit because MIPS has 32 registers, 2^5 = 32).
So having 6 bits for the opcode means only that you are able to encode up to 2^6=64 different instructions which can be interpreted in a single decode cycle.