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20
Devhide
2025-01-07 15:45:07
9.4k
Views
Range of immediate values in ARMv8 A64 assembly
Published on
07 January 2025 at 15:45
#assembly
#arm64
#gnu-assembler
#immediate-operand
55.4k
Views
Is it possible to multiply by an immediate with mul in x86 Assembly?
Published on
07 January 2025 at 15:48
#assembly
#x86
#dos
#multiplication
#immediate-operand
643
Views
How "Immediate" Work In MIPS Architecture?
Published on
07 January 2025 at 15:43
#assembly
#mips
#cpu-architecture
#immediate-operand
244
Views
Integer overflow in gas
Published on
07 January 2025 at 15:41
#assembly
#x86
#x86-64
#gnu-assembler
#immediate-operand
101
Views
Is there a set format on how immediates are shown in RISC-V assembly?
Published on
07 January 2025 at 15:48
#assembly
#riscv
#immediate-operand
2.3k
Views
Confusion about MIPS I-type instruction sign extend
Published on
02 January 2025 at 20:31
#assembly
#mips
#mars-simulator
#sign-extension
#immediate-operand
1.1k
Views
Definition question in Assembly (RiscV), help me understand
Published on
07 January 2025 at 15:46
#assembly
#mips
#riscv
#machine-code
#immediate-operand
179
Views
Instruction format in direct addressing mode
Published on
07 January 2025 at 15:44
#cpu-architecture
#machine-code
#instruction-set
#immediate-operand
758
Views
RISC-V U-Format instruction immediate confusion
Published on
31 December 2024 at 01:32
#assembly
#riscv
#machine-code
#immediate-operand
#instruction-encoding
441
Views
Why does SSE/AVX lack loading an immediate value?
Published on
07 January 2025 at 15:45
#assembly
#x86
#sse
#instruction-set
#immediate-operand
492
Views
ARM Processor: Checking validity of immediate value (Bit rotation)
Published on
07 January 2025 at 15:48
#assembly
#binary
#arm
#immediate-operand
1.6k
Views
How exactly does the RISC-V immediate encoding notation work?
Published on
07 January 2025 at 15:48
#assembly
#encoding
#riscv
#machine-code
#immediate-operand
7.9k
Views
How does LUI/ORI on MIPS work to create a 32-bit constant value?
Published on
07 January 2025 at 15:48
#assembly
#mips
#instruction-set
#immediate-operand
674
Views
Range of immediates in lui instruction
Published on
07 January 2025 at 15:42
#mips
#instructions
#immediate-operand
2.5k
Views
Why opcode is 6-bit long in MIPS 32 bit Architecture
Published on
07 January 2025 at 15:45
#arm
#mips
#instructions
#opcode
#immediate-operand
3.2k
Views
What's the difference between the x86-64 AT&T instructions movq and movabsq?
Published on
07 January 2025 at 15:49
#assembly
#x86-64
#att
#immediate-operand
313
Views
How many memory references are required by the CPU to execute immediate address instruction and why?
Published on
07 January 2025 at 15:51
#cpu
#addressing-mode
#immediate-operand
1.1k
Views
Loading 16-bit (or bigger) immediate with a Arm inline GCC assembly
Published on
07 January 2025 at 15:48
#assembly
#gcc
#arm
#inline-assembly
#immediate-operand
347
Views
Replace `movss xmm0, cs:dword_5B27420` with `movss xmm0, immediate`
Published on
07 January 2025 at 15:48
#assembly
#x86
#reverse-engineering
#sse
#immediate-operand
154
Views
ARMv7 T3 encoding for adds
Published on
31 December 2024 at 01:24
#assembly
#arm
#thumb
#immediate-operand
#instruction-encoding
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