Question

Range of immediate values in ARMv8 A64 assembly

score 9.3k · Answer 1 · 2015-06-18 00:37:17

9.3k

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Range of immediate values in ARMv8 A64 assembly

Published on 18 June 2015 at 00:37

score 55.3k · Answer 2 · 2013-12-10 15:58:34

55.3k

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Is it possible to multiply by an immediate with mul in x86 Assembly?

Published on 10 December 2013 at 15:58

score 593 · Answer 3 · 2020-09-27 14:40:32

593

Views

How "Immediate" Work In MIPS Architecture?

Published on 27 September 2020 at 14:40

score 192 · Answer 4 · 2020-10-10 03:11:25

192

Views

Integer overflow in gas

Published on 10 October 2020 at 03:11

score 51 · Answer 5 · 2023-10-14 15:08:12

51

Views

Is there a set format on how immediates are shown in RISC-V assembly?

Published on 14 October 2023 at 15:08

score 2.3k · Answer 6 · 2020-12-09 17:26:23

2.3k

Views

Confusion about MIPS I-type instruction sign extend

Published on 09 December 2020 at 17:26

score 1k · Answer 7 · 2020-12-13 18:31:57

1k

Views

Definition question in Assembly (RiscV), help me understand

Published on 13 December 2020 at 18:31

score 132 · Answer 8 · 2020-12-19 07:54:47

132

Views

Instruction format in direct addressing mode

Published on 19 December 2020 at 07:54

score 709 · Answer 9 · 2022-04-15 10:27:47

709

Views

RISC-V U-Format instruction immediate confusion

Published on 15 April 2022 at 10:27

score 396 · Answer 10 · 2022-05-06 17:06:23

396

Views

Why does SSE/AVX lack loading an immediate value?

Published on 06 May 2022 at 17:06

score 479 · Answer 11 · 2021-04-23 07:09:54

479

Views

ARM Processor: Checking validity of immediate value (Bit rotation)

Published on 23 April 2021 at 07:09

score 1.6k · Answer 12 · 2021-05-02 08:48:26

1.6k

Views

How exactly does the RISC-V immediate encoding notation work?

Published on 02 May 2021 at 08:48

score 7.8k · Answer 13 · 2018-11-14 17:37:35

7.8k

Views

How does LUI/ORI on MIPS work to create a 32-bit constant value?

Published on 14 November 2018 at 17:37

score 660 · Answer 14 · 2018-11-25 13:20:34

660

Views

Range of immediates in lui instruction

Published on 25 November 2018 at 13:20

score 2.5k · Answer 15 · 2020-09-01 15:16:17

2.5k

Views

Why opcode is 6-bit long in MIPS 32 bit Architecture

Published on 01 September 2020 at 15:16

score 3.2k · Answer 16 · 2018-09-20 22:14:30

3.2k

Views

What's the difference between the x86-64 AT&T instructions movq and movabsq?

Published on 20 September 2018 at 22:14

score 298 · Answer 17 · 2021-05-20 17:26:29

298

Views

How many memory references are required by the CPU to execute immediate address instruction and why?

Published on 20 May 2021 at 17:26

score 1k · Answer 18 · 2021-05-29 23:59:13

1k

Views

Loading 16-bit (or bigger) immediate with a Arm inline GCC assembly

Published on 29 May 2021 at 23:59

score 333 · Answer 19 · 2022-03-09 03:42:13

333

Views

Replace `movss xmm0, cs:dword_5B27420` with `movss xmm0, immediate`

Published on 09 March 2022 at 03:42

score 140 · Answer 20 · 2022-03-19 08:07:06

140

Views

ARMv7 T3 encoding for adds

Published on 19 March 2022 at 08:07

List Question

Range of immediate values in ARMv8 A64 assembly

Is it possible to multiply by an immediate with mul in x86 Assembly?

How "Immediate" Work In MIPS Architecture?

Integer overflow in gas

Is there a set format on how immediates are shown in RISC-V assembly?

Confusion about MIPS I-type instruction sign extend

Definition question in Assembly (RiscV), help me understand

Instruction format in direct addressing mode

RISC-V U-Format instruction immediate confusion

Why does SSE/AVX lack loading an immediate value?

ARM Processor: Checking validity of immediate value (Bit rotation)

How exactly does the RISC-V immediate encoding notation work?

How does LUI/ORI on MIPS work to create a 32-bit constant value?

Range of immediates in lui instruction

Why opcode is 6-bit long in MIPS 32 bit Architecture

What's the difference between the x86-64 AT&T instructions movq and movabsq?

How many memory references are required by the CPU to execute immediate address instruction and why?

Loading 16-bit (or bigger) immediate with a Arm inline GCC assembly

Replace `movss xmm0, cs:dword_5B27420` with `movss xmm0, immediate`

ARMv7 T3 encoding for adds

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