write_verilog without instance names in Yosys

Question

I am trying to use the write_verilog command to generate the nestlist without containing any cell names; rather, only with the verilog expressions. I try the following:

write_verilog -noexpr synth_001.v

But I still get the cell instances (names) in my generated netlist, which I don't want.

To clarify better, for example, in the generated synth_001.v, if I have

  XOR2X1 _207_ (
    .A(_006_),
    .B(_070_),
    .Y(_134_)   );

I would actually like the following:

assign _134_ = _006_ ^ _070_;

I have gone through the Yosys manual, even tried options available from google, like

rename -enumerate

but no luck yet.

Any tips/ideas will be highly appreciated.

Thanks!

Answer 1

Don't use -noexpr when writing verilog file.

write_verilog synth_001.v