XMEGA128A1U Not match Baudrate

Question

I'm using the atxmega128a1 chip, and I got 16m from the external crystal osc and multiplied it by 2 through PLL, giving the clock to 32M inside.

I set the baud rate of USART to 9600, but when I checked in the hyperterminal environment after running, other baud rates are showing strange values, and when I set it to 600, I can check the data I sent.

Even if you change the baudrate value, I don't know what's wrong with the baudrate corresponding to /16 of the changed value being read from the terminal.

There is a corresponding setup code below. I'd appreciate it if you could check it out.

Synchronous asynchronous change in userart is the same symptom. There is no patty bit, 8 bits and stop bit is 1.

• If you straighten 16m with an external crystal without going through pll, the hyperterminal baudrate works normally at 1200.

int8_t OSC_init()
{

    OSC.XOSCCTRL = OSC_FRQRANGE_12TO16_gc        /* 12 - 16 MHz */
                   | 0 << OSC_X32KLPM_bp         /* 32.768 kHz XTAL OSC Low-power Mode: disabled */
                   | 1 << OSC_XOSCPWR_bp         /* Crystal Oscillator Drive: enabled */
                   | OSC_XOSCSEL_XTAL_16KCLK_gc; /* 0.4-16 MHz XTAL - 16K CLK */

    // OSC.XOSCFAIL = 0 << OSC_PLLFDIF_bp /* PLL Failure Detection Interrupt Flag: disabled */
    //       | 0 << OSC_XOSCFDIF_bp; /* XOSC Failure Detection Interrupt Flag: disabled */

    // ccp_write_io((void*)&(OSC.XOSCFAIL),0 << OSC_PLLFDEN_bp /* PLL Failure Detection Enable: disabled */
    //       | 0 << OSC_XOSCFDEN_bp /* XOSC Failure Detection Enable: disabled */);

    // OSC.RC32KCAL = 0; /* Oscillator Calibration Value: 0 */

    OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc    /* External Crystal Oscillator 0.4-16MHz */
                  | 0 << OSC_PLLDIV_bp  /* PLL divided output: disabled */
                  | 2 << OSC_PLLFAC_gp; /* PLL Multiplication Factor: 2 */

    // OSC.CTRL = 0 << OSC_PLLEN_bp /* PLL Enable: disabled */
    //       | 0 << OSC_XOSCEN_bp /* External Oscillator Enable: disabled */
    //       | 0 << OSC_RC32KEN_bp /* Internal 32kHz RC Oscillator Enable: disabled */
    //       | 0 << OSC_RC32MEN_bp /* Internal 32MHz RC Oscillator Enable: disabled */
    //       | 1 << OSC_RC2MEN_bp; /* Internal 2MHz RC Oscillator Enable: enabled */

    // Wait for the Oscillators to be stable

    while (!(OSC.STATUS & OSC_RC2MRDY_bm)) {
        /* Wait for 2MHz Internal Oscillator to be stable */
    }

    // OSC.DFLLCTRL = OSC_RC32MCREF_RC32K_gc /* Internal 32.768 kHz RC Oscillator */
    //       | 0 << OSC_RC2MCREF_bp; /* DFLL 2 MHz DFLL Calibration Reference Enable: disabled */

    // DFLLRC32M.COMP1 = 0; /* DFLL Compare register 1: 0 */

    // DFLLRC32M.COMP2 = 0; /* DFLL Compare register 2: 0 */

    DFLLRC32M.CTRL = 1 << DFLL_ENABLE_bp; /* DFLL Enable: enabled */

    return 0;
}

int8_t CLK_init()
{

    ccp_write_io((void *)&(CLK.CTRL), CLK_SCLKSEL_PLL_gc /* PLL */);

    // ccp_write_io((void*)&(CLK.PSCTRL),CLK_PSADIV_1_gc /* Divide by 1 */
    //       | CLK_PSBCDIV_1_1_gc /* Divide B by 1 and C by 1 */);

    ccp_write_io((void *)&(CLK.LOCK), 1 << CLK_LOCK_bp /* Clock System Lock: enabled */);

    // CLK.RTCCTRL = CLK_RTCSRC_TOSC_gc /* 1.024 kHz from 32.768 kHz crystal oscillator */
    //       | 0 << CLK_RTCEN_bp; /* RTC Clock Source Enable: disabled */

    // CLK.USBCTRL = 0 << CLK_USBPSDIV_gp /* Prescaler Division Factor: 0 */
    //       | CLK_USBSRC_PLL_gc /* PLL */
    //       | 0 << CLK_USBSEN_bp; /* Clock Source Enable: disabled */

    return 0;
}

int8_t USART_F1_DEBUG_init()
{

    int8_t   exp;
    uint32_t div;
    uint32_t cpu_hz = F_CPU;
    uint32_t baud   = 9600;


    /* BSEL = fPER/2*fBAUD - 1 */
    div = cpu_hz / (2 * baud) - 1;
    exp = 0;

    USARTF1.BAUDCTRLB = (uint8_t)(((div >> 8) & 0X0F) | (exp << 4));
    USARTF1.BAUDCTRLA = (uint8_t)div;

    USARTF1.CTRLC = USART_PMODE_DISABLED_gc       /* No Parity */
                    | 0 << USART_SBMODE_bp        /* Stop Bit Mode: disabled */
                    | USART_CHSIZE_8BIT_gc        /* Character size: 8 bit */
                    | 0 << USART_CHSIZE2_bp       /* SPI Master Mode, Data Order: disabled */
                    | 1 << USART_CHSIZE1_bp       /* SPI Master Mode, Clock Phase: enabled */
                    | USART_CMODE_SYNCHRONOUS_gc; /* Sync Polled Mode */

    USARTF1.CTRLB = 1 << USART_CLK2X_bp   /* Double transmission speed: enabled */
                    | 0 << USART_MPCM_bp  /* Multi-processor Communication Mode: disabled */
                    | 1 << USART_RXEN_bp  /* Receiver Enable: enabled */
                    | 1 << USART_TXEN_bp; /* Transmitter Enable: enabled */

    return 0;
}