We have an embedded system that uses a Zynq Ultra Scale (Zu3+) and a microSD card interface. The Zynq project is setup for 3.3V IO using SD 2.0 standards no level shifters. Our manufacturing process uses the SD card to load QSPI and finalize the card for secure boot process. We have several boards that fail to boot from SD or fail during the SD card driver launch (when booted from QSPI). We have captured many scope waveforms of the whole initialization and identification process during OS driver launch (as well as during the boot process). Verified 3.3V startup ramp and SD card signal integrity. Recently we have enabled verbose flags to the driver to log where it is failing. Driver is = devb-sdmmc-xzynq 1.00A. OS is QNX although during SD card boot it is the Xilinx boot loader (PMU).
Basically we see CMD0,8,55,41 get sent out and receive a 0xFF8000 response. This CMD55/41 repeats 500 times while it attempts to change the clock speed and the voltage detection until it eventually times out and says "unsupported card inserted". Same card will also work at times. Makes no difference between a standard SD card or a high speed card. We have a support ticket into Xilinx but I have a feeling they are going to say it is not a Xilinx problem.
We do have different designs that do not have this problem (but use a level shifter and full-size SD cards) as well as one that is almost identical (3.3V microSD) also not having the problem. So trying to say we do have experience with the Zynq firmware and in doing layout. Not sure why these are not also having problems. We have worked closely with the contract manufacturer to analyze the BGA soldering process as well.
One recent observation is when booting from QSPI, and the driver launch fails to mount the SD card... we can "hot swap" the SD card in and the driver will ~mostly launch successfully. This lead us to investigate the 3.3V power ramp (~3ms) which is within spec. Issue is we can't do this during SD card boot which is currently required to program the QSPI and setup the secure boot process.
We have
- tried various MFG SD cards and types (standard SD and high-speed SD which detect the speed properly [HS versus LS] but still timeout)
- Investigated signal integrity on all the SD lines
- Investigated init/ident process on cmd/clk waveforms
- Verified power supply ramp rates and stability
- Supplier did xray verification and "die-and-pry" analysis on BGA connection
- Added verbose information on devb-sdmmc-xzynq (to match scope sequence) to see driver response
- tweaked UCD power sequence to provide additional POR delay
- open and ongoing ticket with Xilinx
- fails more often during SD card boot. May fail during QNX driver launch (only way to get log info)
Hoping for some guidance on how to debug this further and any next steps to try.
Here is some info from latest log file (sorry bad formatting): Jan 01 00:09:50.235 devb_sdmmc_xzynq.1843228 slog* 1800 devb-sdmmc-xzynq 1.00C (Mar 15 2023 10:15:46) Jan 01 00:09:50.239 devb_sdmmc_xzynq.1843228 slog 0 libcam.so (Feb 28 2020 08:43:56) bver 7010001 Jan 01 00:09:50.239 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_pwr: hc->vdd 0x0 vdd 0x0 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cd: insertion path 0, cd state 0x1 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdio_pwr: vdd 0.0 (0x0) Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_pwr: hc->vdd 0x0 vdd 0x0 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdio_pwr: vdd 3.3 (0x200000) Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_pwr: hc->vdd 0x0 vdd 0x200000 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdio_clock: clk 400000 hc_clk_max: 200000000 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdio_clock: setting clock to: 400000 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_clk: clk 400000 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_clk: hc clk max 200000000 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_clk: hc version 2 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_clk: sdhc clk_mul 0 Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_clk: 10 bit divided clock mode Jan 01 00:09:50.241 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_clk: clock divisor 250 Jan 01 00:09:50.245 devb_sdmmc_xzynq.1843228 slog 1800 sdio_bus_width: width 1 Jan 01 00:09:50.245 devb_sdmmc_xzynq.1843228 slog 1800 sdio_timing: timing LS Jan 01 00:09:50.245 devb_sdmmc_xzynq.1843228 slog 1800 sdio_bus_mode: mode open drain Jan 01 00:09:50.245 devb_sdmmc_xzynq.1843228 slog 1800 sdio_signal_voltage: 3.3V Jan 01 00:09:50.262 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.262 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.262 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.262 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.262 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.262 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.262 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 41, flgs 0x812, arg 0x0, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 41, flgs 0x812, arg 0x0, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sd_app_send_op_cond: retries 0, status 0 rsp0 0xff8000 Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sdio_pwr: vdd 3.2 (0x100000) Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_pwr: hc->vdd 0x200000 vdd 0x100000 Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sd_init_device: ocrin: 0x100000, flgs: 0x0 Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.263 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.264 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.264 devb_sdmmc_xzynq.1843228 slog 1800 sd_init_device: sd_app_send_op_cond prep: ocr: 0x40100000 Jan 01 00:09:50.264 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.264 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.264 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.264 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.264 devb_sdmmc_xzynq.1843228 slog 1800 sd_app_send_op_cond: status 0, rsp0 0xff8000 Jan 01 00:09:50.275 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.275 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.275 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms Jan 01 00:09:50.275 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:09:50.275 devb_sdmmc_xzynq.1843228 slog 1800 sd_app_send_op_cond: status 0, rsp0 0xff8000 ... Jan 01 00:10:13.816 devb_sdmmc_xzynq.1843228 slog 1800 sd_app_send_op_cond: status 0, rsp0 0xff8000 Jan 01 00:10:13.827 devb_sdmmc_xzynq.1843228 slog 1800 sd_app_send_op_cond: retries 500, status 0 rsp0 0xff8000 Jan 01 00:10:13.827 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms Jan 01 00:10:13.827 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, status SUCCESS (1) Jan 01 00:10:13.827 devb_sdmmc_xzynq.1843228 slog 1800 sdio_issue_cmd: CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms Jan 01 00:10:13.828 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cmd_cmplt: CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, status CMD TO ERR (5) Jan 01 00:10:13.828 devb_sdmmc_xzynq.1843228 slog 1800 sdio_pwr: vdd 0.0 (0x0) Jan 01 00:10:13.828 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_pwr: hc->vdd 0x100000 vdd 0x0 Jan 01 00:10:13.829 devb_sdmmc_xzynq.1843228 slog 1800 sdio_cd: Unsupported card inserted Jan 01 00:10:13.829 devb_sdmmc_xzynq.1843228 slog 1800 sdhci_pwr: hc->vdd 0x0 vdd 0x0