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List Question
19
Devhide
2024-12-31 10:15:28
597
Views
How to access XDMA BAR0 in Petalinux?
Published on
31 December 2024 at 10:15
#xilinx
#dma
#zynq
#petalinux
#zynq-ultrascale+
168
Views
Is it possible to extract the clk frequency to the CPU on ZC702 eval board (Zynq-7000 XC7Z020 SoC)?
Published on
31 December 2024 at 10:26
#c
#embedded
#xilinx
#zynq-ultrascale+
544
Views
UIO device no longer opens when an interrupt is added
Published on
31 December 2024 at 10:20
#linux
#linux-device-driver
#zynq-ultrascale+
284
Views
Value is wrong first time pointer is dereferenced but correct after that
Published on
31 December 2024 at 10:24
#c
#arm
#xilinx
#cortex-a
#zynq-ultrascale+
207
Views
Why FreeRTOS requires stop once in a breakpoint to run well?
Published on
31 December 2024 at 10:21
#embedded
#breakpoints
#freertos
#zynq-ultrascale+
251
Views
Xilinx Ultrascale UART not found on Big Sur
Published on
31 December 2024 at 10:16
#macos
#uart
#macos-big-sur
#zynq-ultrascale+
47
Views
how to simulate JTAG by SPI in zynq
Published on
31 December 2024 at 10:14
#c
#arm
#spi
#jtag
#zynq-ultrascale+
2.4k
Views
How to find dma_request_chan() failure reason details?
Published on
31 December 2024 at 10:19
#linux-kernel
#linux-device-driver
#embedded-linux
#xilinx
#zynq-ultrascale+
4k
Views
How to access Xilinx Axi DMA from Linux?
Published on
31 December 2024 at 10:14
#xilinx
#dma
#petalinux
#xilinx-edk
#zynq-ultrascale+
302
Views
PROFIBUS Architecture for Ultrascale +: experts' opinion request
Published on
31 December 2024 at 10:23
#protocols
#master-slave
#rs485
#industrial
#zynq-ultrascale+
1.4k
Views
Why are the headers not found in the Xilinx SDK?
Published on
31 December 2024 at 10:18
#c++
#linux
#eclipse-cdt
#xilinx
#zynq-ultrascale+
125
Views
Cross-Compilation of Point Cloud Library for ARM Cortex R5
Published on
31 December 2024 at 10:21
#xilinx
#point-cloud-library
#vitis-ai
#zynq-ultrascale+
#cortex-r
348
Views
How to access ethernet ports from both RPU and APU?
Published on
31 December 2024 at 10:19
#embedded-linux
#xilinx
#freertos
#vitis-ai
#zynq-ultrascale+
64
Views
How to trigger a software generated interrupt on core1 from core1 on bare metal?
Published on
31 December 2024 at 10:25
#interrupt
#xilinx
#zynq
#zynq-ultrascale+
37
Views
zynqmp ptp clock adjustment
Published on
31 December 2024 at 10:11
#linux-kernel
#ptp
#zynq-ultrascale+
#zynqmp
195
Views
Zynq PetaLinux system PL needs to write to PS RAM - how do I provide PL with the correct physical address?
Published on
31 December 2024 at 10:27
#mmap
#memory-mapping
#zynq-ultrascale+
505
Views
What is the reason I get this error using bootgen?
Published on
31 December 2024 at 10:18
#interrupt
#xilinx
#zynq-ultrascale+
708
Views
Silabs Si5340: how to define a clock for one of the chip outputs
Published on
31 December 2024 at 10:23
#linux-kernel
#clock
#device-tree
#petalinux
#zynq-ultrascale+
228
Views
Zynq Ultrascale (ZU3+) failing SD card init/ident process = "unsupported card inserted"
Published on
31 December 2024 at 10:25
#sd-card
#qnx
#zynq-ultrascale+
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