DEVHIDE
Login Or Sign up

List Question

19
604
Views

How to access XDMA BAR0 in Petalinux?

Published on
#xilinx #dma #zynq #petalinux #zynq-ultrascale+
177
Views

Is it possible to extract the clk frequency to the CPU on ZC702 eval board (Zynq-7000 XC7Z020 SoC)?

Published on
#c #embedded #xilinx #zynq-ultrascale+
553
Views

UIO device no longer opens when an interrupt is added

Published on
#linux #linux-device-driver #zynq-ultrascale+
293
Views

Value is wrong first time pointer is dereferenced but correct after that

Published on
#c #arm #xilinx #cortex-a #zynq-ultrascale+
216
Views

Why FreeRTOS requires stop once in a breakpoint to run well?

Published on
#embedded #breakpoints #freertos #zynq-ultrascale+
259
Views

Xilinx Ultrascale UART not found on Big Sur

Published on
#macos #uart #macos-big-sur #zynq-ultrascale+
56
Views

how to simulate JTAG by SPI in zynq

Published on
#c #arm #spi #jtag #zynq-ultrascale+
2.4k
Views

How to find dma_request_chan() failure reason details?

Published on
#linux-kernel #linux-device-driver #embedded-linux #xilinx #zynq-ultrascale+
4k
Views

How to access Xilinx Axi DMA from Linux?

Published on
#xilinx #dma #petalinux #xilinx-edk #zynq-ultrascale+
312
Views

PROFIBUS Architecture for Ultrascale +: experts' opinion request

Published on
#protocols #master-slave #rs485 #industrial #zynq-ultrascale+
1.4k
Views

Why are the headers not found in the Xilinx SDK?

Published on
#c++ #linux #eclipse-cdt #xilinx #zynq-ultrascale+
133
Views

Cross-Compilation of Point Cloud Library for ARM Cortex R5

Published on
#xilinx #point-cloud-library #vitis-ai #zynq-ultrascale+ #cortex-r
355
Views

How to access ethernet ports from both RPU and APU?

Published on
#embedded-linux #xilinx #freertos #vitis-ai #zynq-ultrascale+
72
Views

How to trigger a software generated interrupt on core1 from core1 on bare metal?

Published on
#interrupt #xilinx #zynq #zynq-ultrascale+
43
Views

zynqmp ptp clock adjustment

Published on
#linux-kernel #ptp #zynq-ultrascale+ #zynqmp
201
Views

Zynq PetaLinux system PL needs to write to PS RAM - how do I provide PL with the correct physical address?

Published on
#mmap #memory-mapping #zynq-ultrascale+
511
Views

What is the reason I get this error using bootgen?

Published on
#interrupt #xilinx #zynq-ultrascale+
716
Views

Silabs Si5340: how to define a clock for one of the chip outputs

Published on
#linux-kernel #clock #device-tree #petalinux #zynq-ultrascale+
235
Views

Zynq Ultrascale (ZU3+) failing SD card init/ident process = "unsupported card inserted"

Published on
#sd-card #qnx #zynq-ultrascale+

Trending Questions

Popular # Hahtags

javascript python java c# php android html jquery c++ css ios sql mysql r reactjs node.js arrays c asp.net json python-3.x ruby-on-rails .net sql-server swift django angular objective-c pandas excel

Popular Questions

Copyright © 2021 Jogjafile Inc.