4-bit ALU using 1-bit ALU in verilog

Question

I have a project to build a 4-bit ALU using a 1-bit ALU, I already created. The 1-bit ALU works perfectly but I can't figure out how to put them together. Here's the 1-bit and 4-bit code, as well as the testbench. I keep getting a syntax error about mismatching "endmodule" in my testbench.

4-Bit:

module FourBitALU(a, b, op, result, cout);
  input [3:0] a, b; 
  input [3:0] op;
  
  output [3:0] result;
  output cout;
  reg[3:0]result;
  reg [3:0] sum;
  wire cout;
  
  OneBitALU oba0(a[0], b[0], 0, op[3], op[2], 0, op[1:0], result[0], cout, sum[0]);
  OneBitALU oba1(a[1], b[1], cout, op[3], op[2], 0, op[1:0], result[1], cout, sum[1]);
  OneBitALU oba2(a[2], b[2], cout, op[3], op[2], 0, op[1:0], result[2], cout, sum[2]);
  OneBitALU oba3(a[3], b[3], cout, op[3], op[2], 1, op[1:0], result[3], cout, sum[3]);
  
  
endmodule

1-Bit:

module OneBitALU(a, b, cin, ainv, binv, less, op, result,
cout, set);
  input a, b, cin;
  input ainv, binv;
  input less;
  input [1:0] op;
  
  output result;
  output cout;
  output set;
  wire aneg, bneg;
  
  reg result;  
  assign aneg = ainv ? ~a : a;
  assign bneg = binv ? ~b : b;
  
  FullAdder fulladder(aneg, bneg, cin, set, cout);
  
  always @ (*) begin
    case(op)
      2'b00: result = aneg & bneg;
      2'b01: result = aneg | bneg;
      2'b10: result = set;
      2'b11: begin
        case(less)
          1'b0: result = 0;
          1'b1: result = (a < b) ? 1 : 0;
        endcase
      end
      default: result = 1'b0;   
    endcase
  end
endmodule

Testbench:

`timescale 1ns / 1ps
`include "4bitalu.sv"

module FourBitALU_testbench;

  parameter DELAY = 10;

  reg [3:0] a, b;
  reg [3:0] op;
  
  wire[3:0] result;
  wire cout;
  
  FourBitALU test_unit(
    .a(a), 
    .b(b), 
    .op(op), 
    .result(result), 
    .cout(cout)
  );
  
  initial begin
    $dumpfile("FourBitALU_testbench.vcd");
    $dumpvars(0, FourBitALU_testbench);
    
    a = 4'b0101;
    b = 4'b0011;
    op = 4'b0001;
    #DELAY
    
    a = 4'b0101;
    b = 4'b0011;
    op = 4'b0010;
    #DELAY
    
    a = 4'b0101;
    b = 4'b0011;
    op = 4'b0011;
    #DELAY
    
    a = 4'b0101;
    b = 4'b0011;
    op = 4'b0100;
    #DELAY
    
    a = 4'b0101;
    b = 4'b0011;
    op = 4'b0101;
    #DELAY
    
    a = 4'b0101;
    b = 4'b0011;
    op = 4'b0110;
    #DELAY
    
    a = 4'b0101;
    b = 4'b0011;
    op = 4'b0111;
    #DELAY
    
    a = 4'b0101;
    b = 4'b0011;
    op = 4'b1000;
    #DELAY
    
    //MORE TEST CASES

    $finish
  end
endmodule

I honestly have no clue how to get it to run, let alone make it subtract.