How to compile only the changed files in Verilator?

Question

I use Verilator to compile and simulate my design. The whole compilation and simulation takes forever. Since I am testing a feature, I only change one module in the design every time. I want know if there is a way to only compile the changed file instead of the entire design every time.

For e.g. if my hierarchy is this

      TOP
      / \
     A   B
    / \
  a1  a2

I only change a2. So I want Verilator to only compile a2 again instead of the entire design.