AMD/Xilinx SystemVerilog class variables disappeared in sript vs. project simulation

Question

While scripting one of the SystemVerilog class-based testbenches I noticed that the testbench (code below) level variables are not visible in Vivado Objects tab. These variables are visible in the project based flow (please see two images).

class tb;

virtual my_bfm bfm;

tester     tester_h;
coverage   coverage_h;
scoreboard scoreboard_h;

function new (virtual my_bfm b);
  bfm = b;
endfunction : new

task execute();
  tester_h     = new(bfm);
  coverage_h   = new(bfm);
  scoreboard_h = new(bfm);

  fork
    coverage_h.execute();
    scoreboard_h.execute();
    tester_h.execute();
  join_none
endtask : execute

endclass : tb

In addition to comparing all options for xvlog and xelab, I compared both scripted and project xelab --verbose logs. I could not find differences that may explain this. I suspect there is some class related environment variable that is set in a project flow vs. script.

Can anyone help to reveal what it is or suggest another solution?