I wanted to develop a high speed data transmission serial communication protocol, for a adc/dac link using spartan 6 fpga programmed in xilinx ise (14.7), so I wanted to increase speed of internal clock (provided as spartan 6 has 100Mhz clock at peripheral) using clock wizard. I have a transmission protocol based on uart, I am able to receive data bits successfully for upto 405 Mhz using clock wizard, above that it is asking to use buffpll and implementing it, i am not able to recieve frames at reciever...
What could be the possible error and solution to it ?
I tried developing but the channel is not visible at reciever's side ...