I wondering how the cache subsystem will act in the following situation: Let's consider Cortex-a8 and VIPT L1-cache. Suppose a cacheable virtual memory mapping [A,B] was created, for some time the one worked with this memory region so the data cache was filled up. After this, suppose, the mapping [A,B] was substituted by uncacheable. After that we perform a flush operation (DCCIMVAC) on virtual region [A,B]. What will happen in this situation? The cache data will be just discarded (invalidated)? Or data will be flushed to non cacheable pages anyway? Or something else?
Update:
The main reason why I'am asking is - my board stucks immediately after one of this flush instructions in the context I described above. I just have no idea why this could happen. More literally, it hangs in the middle of the page, flushing one of the cache lines at the offset 0xd80. If skip this cache line flush - it goes further. If change attrs to cacheable (from uncacheable) it works ok. And looks like it should be changed to cacheable, but I try to figure out what this code had done. I'am mostly interested in - if the scenario I had described is legal, or it may lead to some undefined behavior.