Wrong core register layout when context switching in uc/os-III

Question

uC/OS-III says:

When calling OSTaskCreate(), uC/OS-III initializes the top of the task's stack with a copy of the CPU register in the same stacking order as if they were all saved at the beginning of an ISR.

Here is the arm Complete ARM register set.

FYI: I'm using cortex-a8 which is based on v7 architecture, but I believe that v7 core's register layout is the same as following image Here is the debug info before executing OSTaskCreate statement: Here is the debug info after executing OSTaskCreate statement: It's obvious that these values the stack saves is totally different from core register.

How could it be?

Answer 1

This is probably the reference you need, context switching, indicating that SR/PC are saved first, then the other registers r0-r13. For a definative answer, you can refer to the source in os_cpu_a.asm.