Cannot understand the errors in my code

Question

I'm working on t-bird lights controller and I keep getting these errors in my code and when I go through the code there is nothing really wrong with it! I don't have much experience in VHDL but I can tell if it is right or wrong, please I need your help

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;

 entity tbird is
 PORT(clk, lts,rts,haz,brake: IN bit;
 lc,lb,la,ra,rb,rc: OUT bit);
 end tbird;

 architecture one of tbird is
 TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3,lr4);
 signal state ,next_state: state_type;
 BEGIN
 process 
 BEGIN
 WAIT UNTIL clk='1' AND clk'event;
 state <= next_state;
 end process;
 --next state generation
 PROCESS(state,rts,lts,haz,brake)
 begin
 case state is
 WHEN idle => 
 IF(haz='1' OR (lts='1' AND rts='1' AND break='0')) Then next_state <= lr3;
  elsif (haz ='0' AND lts='0' and brake='0' and rts='1') then next_state <= r1;
  elsif (haz ='0' and lts='1' and brake='0' and rts='0') then next_state <= l1;
  elsif (haz='0' and lts='0' and brake='1' and rts='0') then next_state <= lr4;
  else next_state <= idle;
  end if;

 WHEN l1=> IF(haz='1') THEN next_state <= lr3;
  elsif (brake='1') then next_state <= lr4;
  ELSE next_state <= l2;
  END IF;

 WHEN l2=> 
  IF(haz='1') THEN next_state<= lr3;
  elsif(brake ='1') then next_state <= lr4;
  ELSE next_state <= l3;
  END IF;

 WHEN l3=>
  next_state <=idle;

 WHEN r1=>IF(haz='1') THEN next_state <= lr3;
  elsif(brake='1') then next_state <= lr4;
  ELSE next_state <= r2;
  END IF;


 WHEN r2=>IF(haz='1') THEN next_state <= lr3;
  IF(brake='1') THEN next_state <= lr4;
  ELSE next_state <= r3;
  END IF;
  WHEN r3=> next_state <= idle;

  WHEN lr3=> next_state <= idle;
  WHEN lr4=>IF(brake='1')next_state <=lr4;
  else next_state <= idle;
  END case;
  END PROCESS;


 PROCESS(state)
 BEGIN
  case state is
  WHEN idle => lc<='0'; lb<='0'; la<='0';ra<='0'; rb <='0'; rc<='0';
  WHEN l1 => lc<='0'; lb<='0'; la<='1';ra<='0'; rb <='0'; rc<='0';
  WHEN l2 => lc<='0'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN l3 => lc<='1'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN r1 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='0'; rc<='0';
  WHEN r2 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='0';
  WHEN r3 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='1';
  WHEN lr3 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1'; 
  WHEN lr4 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1';
 END case;
 END PROCESS;
 END one;    

These are the errors

 INFO:HDLCompiler:1061 - Parsing VHDL file "D:/ISE/DSD LABS/assigment/brake.vhd" into library work
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 53: Syntax error near "WHEN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 55: Syntax error near "WHEN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 56: Syntax error near "WHEN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 58: Syntax error near "case".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 63: Syntax error near "BEGIN".
 ERROR:HDLCompiler:806 - "D:/ISE/DSD LABS/assigment/brake.vhd" Line 75: Syntax error near "PROCESS".
 ERROR:ProjectMgmt - 6 error(s) found while parsing design hierarchy.

Answer 1

in the line : WHEN lr4=>IF(brake='1')next_state <=lr4;

The word THEN is missing.

Answer 2

In the following code rename "break" to "brake". You declared "brake" in the entity :

IF(haz='1' OR (lts='1' AND rts='1' AND break='0')) Then next_state <= lr3;

In the following code add end if; statement at the end of line :

WHEN r2=>IF(haz='1') THEN next_state <= lr3;

In the following code use then and end if; statements in the right place :

WHEN lr4=>IF(brake='1')next_state <=lr4;
    else next_state <= idle;
END case;

With the above changes the syntax errors will be removed.

Answer 3

Note your error message Line numbers don't match your VHDL code example.

The things keeping your VHDL example from analyzing:

architecture one of tbird is
 TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3,lr4);
 signal state ,next_state: state_type;
 BEGIN
 process 
 BEGIN
 WAIT UNTIL clk='1' AND clk'event;
 state <= next_state;
 end process;
 --next state generation
 PROCESS(state,rts,lts,haz,brake)
 begin
 case state is
 WHEN idle =>  -- brake NOT break
 IF(haz='1' OR (lts='1' AND rts='1' AND brake='0')) Then next_state <= lr3;
  elsif (haz ='0' AND lts='0' and brake='0' and rts='1') then next_state <= r1;
  elsif (haz ='0' and lts='1' and brake='0' and rts='0') then next_state <= l1;
  elsif (haz='0' and lts='0' and brake='1' and rts='0') then next_state <= lr4;
  else next_state <= idle;
  end if;

 WHEN l1=> IF(haz='1') THEN next_state <= lr3;
  elsif (brake='1') then next_state <= lr4;
  ELSE next_state <= l2;
  END IF;

 WHEN l2=> 
  IF(haz='1') THEN next_state<= lr3;
  elsif(brake ='1') then next_state <= lr4;
  ELSE next_state <= l3;
  END IF;

 WHEN l3=>
  next_state <=idle;

 WHEN r1=>IF(haz='1') THEN next_state <= lr3;
  elsif(brake='1') then next_state <= lr4;
  ELSE next_state <= r2;
  END IF;


 WHEN r2=>IF(haz='1') THEN next_state <= lr3;
  ELSIF(brake='1') THEN next_state <= lr4;  -- ELSIF was IF
  ELSE next_state <= r3;
  END IF;
  WHEN r3=> next_state <= idle;

  WHEN lr3=> next_state <= idle;
  WHEN lr4=>IF(brake='1')THEN next_state <=lr4; -- MISSING THEN
  else next_state <= idle;
  END IF;                       -- MISSING ENDIF
  END case;
  END PROCESS;


 PROCESS(state)
 BEGIN
  case state is
  WHEN idle => lc<='0'; lb<='0'; la<='0';ra<='0'; rb <='0'; rc<='0';
  WHEN l1 => lc<='0'; lb<='0'; la<='1';ra<='0'; rb <='0'; rc<='0';
  WHEN l2 => lc<='0'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN l3 => lc<='1'; lb<='1'; la<='1';ra<='0';rb <='0'; rc<='0';
  WHEN r1 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='0'; rc<='0';
  WHEN r2 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='0';
  WHEN r3 => lc<='0'; lb<='0'; la<='0';ra<='1';rb <='1'; rc<='1';
  WHEN lr3 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1'; 
  WHEN lr4 => lc<='1'; lb<='1'; la<='1';ra<='1';rb <='1'; rc<='1';
 END case;
 END PROCESS;
 END one;

You used break instead of brake in the choice idle of the second processes case statement.

In choice r2 of the same case statement it appears you intended the second IF to be ELSIF.

In choice lr4 of the same case statement you're missing a THEN before the assignment in the if statement.

You're missing an ENDIF for that same if statement.

You could also note you don't need the context clause (library and use statements before the entity declaration). Your input and output ports are all type BIT and the only other declared signals are type state_type.

This might be what your code would look like prettified:

-- library ieee;                  -- NOT NEEDED
-- use ieee.std_logic_1164.all;   -- NOT NEEDED
-- use ieee.std_logic_arith.all;  -- NOT NEEDED

 entity tbird is
     port (
         clk, lts,rts,haz,brake:    in  bit;
         lc,lb,la,ra,rb,rc:         out bit
     );
 end tbird;

 architecture prettified of tbird is
     type state_type is (idle,l1,l2,l3,r1,r2,r3,lr3,lr4);
     signal state, next_state: state_type;
 begin
STATE_REG:
     process 
     begin
         wait until clk = '1' and clk'event;
         state <= next_state;
     end process;
NEXTSTATE:
    process(state,rts,lts,haz,brake)
    begin
        case state is
            when idle => 
                 if haz = '1' or (lts = '1' and rts = '1' and brake = '0') then -- brake NOT break
                     next_state <= lr3;
                 elsif haz = '0' and lts ='0' and brake ='0' and rts = '1' then 
                     next_state <= r1;
                 elsif haz = '0' and lts = '1' and brake = '0' and rts = '0' then 
                     next_state <= l1;
                 elsif haz = '0' and lts = '0' and brake = '1' and rts = '0' then 
                     next_state <= lr4;
                 else
                     next_state <= idle;
                 end if;
            when l1 => 
                if haz = '1' then 
                    next_state <= lr3;
                elsif brake = '1' then 
                    next_state <= lr4;
                else 
                    next_state <= l2;
                end if;
            when l2 => 
                if haz='1' then 
                    next_state<= lr3;
                elsif brake ='1' then 
                    next_state <= lr4;
                else 
                    next_state <= l3;
                end if;
            when l3 =>
                next_state <=idle;
            when r1 =>
                if haz = '1' then 
                    next_state <= lr3;
                elsif brake = '1' then 
                    next_state <= lr4;
                else 
                    next_state <= r2;
                end if;
            when r2 =>
                if haz = '1' then 
                    next_state <= lr3;
                elsif brake = '1' then  -- WAS if looks like should be elsif
                    next_state <= lr4;
                else 
                    next_state <= r3;
                end if;
            when r3 => 
                next_state <= idle;
            when lr3 => 
                next_state <= idle;
            when lr4 => 
                if brake = '1' then       -- MISSING then
                    next_state <= lr4;
                else 
                    next_state <= idle;
                end if;                 -- MISSING endif
        end case;
    end process;
MOORE_OUTPUTS:    
    process(state)
    begin
        case state is
            when idle =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '0'; rb <= '0'; rc <= '0';
            when l1 =>
                lc <= '0'; lb <= '0'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0';
            when l2 =>
                lc <= '0'; lb <= '1'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0';
            when l3 =>
                lc <= '1'; lb <= '1'; la <= '1'; ra <= '0'; rb <= '0'; rc <= '0';
            when r1 =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '0'; rc <= '0';
            when r2 =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '1'; rc <= '0';
            when r3 =>
                lc <= '0'; lb <= '0'; la <= '0'; ra <= '1'; rb <= '1'; rc <= '1';
            when lr3 =>
                lc <= '1'; lb <= '1'; la <= '1'; ra <= '1'; rb <= '1'; rc <= '1'; 
            when lr4 =>
                lc <= '1'; lb <= '1'; la <= '1'; ra <= '1'; rb <= '1'; rc <= '1';
        end case;
    end process;
end architecture;

The idea being the use of labels prevents you from having to point at things in a circumlocutory manner, consistent use of white space and indentation makes the code easier to read, and I removed the unneeded parentheses pairs.

I'd be tempted to express the MOORE_OUTPUTS process differently using constant arrays indexed by state_type'pos(state). It'd be more compact and as easy to modify. The new declarations could be process statement declarative items (before the begin).

That process might look something like this:

MOORE_OUTPUTS:
    process (state)
    type state_outputs is array (state_type'pos(idle) to state_type'pos(lr4)) 
        of bit_vector(0 to 5);
    constant outputs: state_outputs := ( 
                      -- lc   lb   la   ra   rb   rc
                        ('0', '0', '0', '0', '0', '0'), -- idle
                        ('0', '0', '1', '0', '0', '0'), -- l1
                        ('0', '1', '1', '0', '0', '0'), -- l2
                        ('1', '1', '1', '0', '0', '0'), -- l3
                        ('0', '0', '0', '1', '0', '0'), -- r1
                        ('0', '0', '0', '1', '1', '0'), -- r2
                        ('0', '0', '0', '1', '1', '1'), -- r3
                        ('1', '1', '1', '1', '1', '1'), -- lr3
                        ('1', '1', '1', '1', '1', '1')  -- lr4
                    ); 
    begin
        (lc, lb, la, ra, rb, rc) <= outputs(state_type'pos(state));
    end process;

Which presents a nice table you could manipulate directly.

While I analyzed and elaborated both architectures, neither have been simulated.