Circuit behaves poorly in timing simulation but alright in behavioral - new to verilog

Question

I'm new to verilog development and am having trouble seeing where I'm going wrong on a relatively simple counter and trigger output type design.

Here's the verilog code Note the code returns the same result whether or not the reg is declared on the output_signal without the internal_output_buffer

    `timescale 1ns / 1ps

module testcounter(
        input wire clk,
        input wire resetn,
        input wire [31:0] num_to_count,
        output reg [7:0] output_signal
    );

    reg [31:0] counter;

    initial begin
        output_signal = 0;
    end

    always@(negedge resetn) begin
        counter = 0;
    end

    always@(posedge clk) begin
        if (counter == num_to_count) begin
            counter = 0;
            if (output_signal == 0) begin
                output_signal = 8'hff;
            end
            else begin
                output_signal = 8'h00;
            end
        end
        else begin
            counter = counter + 1;
        end 


    end
    assign output_signal = internal_output_buffer;

endmodule

And the code is tested by

 `timescale 1ns / 1ps

module testcounter_testbench(

    );
    reg clk;
    reg resetn;
    reg [31:0] num_to_count;
    wire [7:0] output_signal;

    initial begin
        clk = 0;
        forever #1 clk = ~clk;
    end

    initial begin
        num_to_count = 20;
    end

    initial begin
        #7 resetn = 1;
        #35 resetn = 0;
    end

    testcounter A1(.clk(clk),.resetn(resetn),.num_to_count(num_to_count),.output_signal(output_signal));
endmodule

Behavioral simulation looks as I expected

But the timing simulation explodes

And for good measure: the actual probed execution blows up and looks like

Any tips would be appreciated. Thanks all.

Answer 1

The difference between the timing and functional simulations is that a timing simulation models the actual delay of logic gates while the functional simulation just checks if values are correct.

For e.g. if you have a simple combinational adder with two inputs a and b, and output c. A functional simulation will tell you that c=a+b. and c will change in the exact microsecond that a or b changes. However, a timing simulation for the same circuit will only show you the result (a+b) on c after some time t, where t is the delay of the adder.

What is your platform? If you are using an FPGA it is very difficult to hit 500 MHz. Your clock statement:

    forever #1 clk = ~clk;

shows that you toggle the clock every 1ns, meaning that your period is 2ns and your frequency is 500MHz.

The combinational delay through FPGA resources such as lookup tables, multiplexers and wire segments is probably more than 2ns. So your circuit violates timing constraints and gives wrong behaviour.

The first thing I would try is to use a much lower clock frequency, for example 100 MHz and test the circuit again. I expect it to produce the correct results.

    forever #5 clk = ~clk;

Then to know the maximum safe frequency you can run at, look at your compilation reports in your design tools by running timing analysis. It is available in any FPGA CAD tool.

Answer 2

Your code seems working fine using Xilinx Vivado 14.2 but there is only one error which is the following line

assign output_signal = internal_output_buffer;

You can't assign registers by using "assign" and also "internal_output_buffer" is not defined.

I also personally recommend to set all registers to some values at initial. Your variables "resetn" and "counter" are not assigned initially. Basicly change your code like this for example

reg [31:0] counter = 32'b0;

Here is my result with your code:

Answer 3

Your verilog code in the testcounter looks broken: (a) you're having multiple drivers, and (b) like @StrayPointer notices, you're using blocking assignments for assigning Register (Flip-Flop) values.

I'm guessing your intent was the following, which could fix a lot of simulation mismatches:

module testcounter
(
    input wire clk,
    input wire resetn,
    input wire [31:0] num_to_count,
    output reg [7:0] output_signal
);

reg [31:0] counter;

always@(posedge clk or negedge resetn) begin
    if (!resetn) begin
        counter <= 0;
    end else begin
        if (counter == num_to_count) begin
            counter <= 0;
        end else begin
            counter <= counter + 1;
        end
    end
end
assign output_signal = (counter == num_to_count) ? 8'hff : 8'h00;

endmodule