Different resource utilization shows in vivado hls and vivado

Question

I implemented this loop calculation in vivado HLS.

For (i = 0; i < 59; i++){
#pragma HLS unroll
    tmp = C[i];
    For (j = 0; j < 3; j++){
#pragma HLS unroll
         tmp = tmp + A[j][i] * B[j];
     }
     C[i] = tmp;
}

The DSP48E utilization result is 189.

I export this module and run the synthesis in vivado.

The DSP48 utilization result is 39.

I want to know why the results are very different?

Answer 1

Please remember, Vivado HLS (High-Level Synthesis) will always provides estimates. It will never ever provide the exact resource utilization as the compiler in Vivado HLS does not perform place and route. Whereas the Vivado synthesis provides you an actual resource utilization.

However, having said that, the amount of DSP48 difference you have mentioned, that's a considerable difference and should not happen. Following are my list of answers for you to tackle this:

• The first and foremost thing you should consider is to make sure you are using the latest versions. Ok, if not latest, at least please make sure the Vivado HLS and Vivado version are the same. There can sometimes be a difference between HLS estimates and the Vivado Synthesis results if you are using different versions.

• Make sure you have selected the identical underlying FPGA hardware.

• You should run the export step of the Vivado HLS flow with Vivado synthesis enabled. This will synthesize the Vivado HLS IP in Vivado Synthesis (not HLS Synthesis) and then return the actual resources used. Please refer to page 108 in this guide. You can read about different synthesis options specifically.

• Vivado synthesis tool does make some physical optimization. For instance please check opt_design optimization in your Vivado.

Answer 2

• Synthesis has detailed knowledge of the target, strategies, and functionality designed to optimize use of resources.

• Synthesis may decide its OK to implement some of the adds as LUT/logic fabric, where HLS makes some sort of assumption like one DSP per add (or something like that).

• Synthesis 'logic trim' parts of buses that are not used downstream. Examine the synthesis result and make sure that the output bus temp is the width you expect.

• Use the Vivado RTL viewer (F4) with the synthesized design open to explore the netlist and verify that bus widths is as expected.