Differentiation of "Vector Load/Store Whole Register Instructions"

Question

In the RISC-V vector extension, instructions are provided to load/store single or multiple vector registers in a single command.

Among these, there are currently four types of load instructions available from memory to v registers, namely vl1re8/16/32/64.v.

However, these four types of instructions share a common range to load, which is determined by the "VLEN bit". For instance, the vl1re8.v instruction stores VLEN/8 [byte] into the vector register, and the vl1re64.v instruction stores VLEN/64[dward] into the register. In other words, the size loaded into the vector register is the same for all four types of instructions.

When VLEN is less than 64, there may be instructions that cannot be used. However, when VLEN is 65 or greater, the results obtained from using any instruction should be essentially the same. The only conceivable reason for this redundancy might be if there were alignment restrictions for loading from memory.

Answer 1

The RVV spec provides an answer to your question:

Because in-register byte layouts are identical to in-memory byte layouts, the same data is written to the destination register group regardless of EEW. Hence, it would have sufficed to provide only EEW=8 variants. The full set of EEW variants is provided so that the encoded EEW can be used as a hint to indicate the destination register group will next be accessed with this EEW, which aids implementations that rearrange data internally

The alignment requirements are also different, the memory needs to be aligned to the EEW.

Allowing misaligned exceptions to be raised based on non-alignment to the encoded EEW simplifies the implementation of these instructions. Some subset implementations might not support smaller SEW widths, so are allowed to report misaligned exceptions for the smallest supported SEW even if larger than encoded EEW. An extreme non-standard implementation might have SEWMIN>XLEN for example. Software environments can mandate the minimum alignment requirements to support an ABI