I am developing a hardware platform that requires the SSSE3 instruction set. When looking at a processor such as the Intel Atom® x5-Z8350 the datasheet says it has support for SSE4.1 and SSE4.2. Would this allow software written for SSSE3 instructions to function?
I believe this question is slightly different than this question as it never explicitly says SSE4 is a superset of SSSE3. It only says AVX is a superset.
This answer is for Intel processors only.
First, all Intel Atom processors from the earliest ones to the most recent ones support SSSE3. Section 1.2.14 of the Intel manual states:
And also Table 5-1 of the manual states:
This is also consistent with Wikipedia.
I'm not sure whether the manual states explicitly that if SSE4 is supported then SSSE3 is supported, but we can derive that.
Section 12.7.3 discusses how to check for SSSE3 support:
also Section 12.12.2 discusses how to check for SSE4.1 support:
and finally Section 12.12.3 discusses how to check for SSE4.2 support:
As you can see, both SSE4.1 and SSE4.1 require support for SSSE3. We can also conclude that SSSE3 requires support for SSE2.
CAVEAT: Most likely this will continue to hold in the future, although it's hard to be sure 100%.
One interesting observation though is when comparing the list of processors that support SSSE3 against the lists of those that support SSE4.1 and SSE4.2 (Table 5-1 and Table 5-2), there is only one processor, Intel Core i7 965 processor, that is in the list of SSE4.2 but not SSSE3, yet the processor actually supports SSSE3. Not sure whether this is an error in the manual, or more horrifyingly, it's incomplete.
Another interesting observation is that, for processors other than Atom (see the quote from Section 1.2.14 above), it seems that support for SSSE3, SSE4.1, or SSE4.2 does not necessarily mean that SSE3 is supported. I didn't find anything in the manual that enables me to make that conclusion. At the same time, I don't know of any processor that supports SSSE3, SSE4.1, or SSE4.2, but not SSE3.
Section 12.1.1 specifies which registers are available in SSSE3:
Section 12.7.1 discusses OS support for SSSE3:
So any OS that requires SSE automatically supports SSSE3.