Question

ARM LL/SC exclusive access by register width or cache line width?

score 2.8k · Answer 1 · 2025-01-07 02:35:39

2.8k

Views

ARM LL/SC exclusive access by register width or cache line width?

Published on 07 January 2025 at 02:35

score 1.6k · Answer 2 · 2025-01-07 02:32:45

1.6k

Views

How does x86 handle store conditional instructions?

Published on 07 January 2025 at 02:32

score 3.4k · Answer 3 · 2025-01-07 02:35:37

3.4k

Views

How do ldrex / strex make atomic_add in ARM an atomic operation?

Published on 07 January 2025 at 02:35

score 1.8k · Answer 4 · 2025-01-07 02:36:22

1.8k

Views

Lock-free C++11 example using Load-link/store-conditional to prevent ABA?

Published on 07 January 2025 at 02:36

score 744 · Answer 5 · 2025-01-07 02:38:24

744

Views

In risc-v architecture, how does store conditional instruction realize that the memory is modified?

Published on 07 January 2025 at 02:38

score 2k · Answer 6 · 2025-01-07 02:36:21

2k

Views

What' s the advantage of LL/SC when compared with CAS (compare-and-swap)?

Published on 07 January 2025 at 02:36

score 631 · Answer 7 · 2025-01-07 02:38:23

631

Views

ARM Cortex-M4/7: Do regular memory accesses between LDREX/STREX invalidate the exclusive monitor

Published on 07 January 2025 at 02:38

score 44 · Answer 8 · 2025-01-05 17:23:32

44

Views

__sync_add_and_fetch triggers an sError interrupt on raspberry pi 4b

Published on 05 January 2025 at 17:23

score 6.7k · Answer 9 · 2025-01-07 02:36:41

6.7k

Views

compare-and-swap atomic operation vs Load-link/store-conditional operation

Published on 07 January 2025 at 02:36

score 2.5k · Answer 10 · 2025-01-07 02:32:03

2.5k

Views

What's 'reservation' in RISC-V's 'lr' instruction?

Published on 07 January 2025 at 02:32

score 386 · Answer 11 · 2025-01-07 02:32:44

386

Views

Implementing global monitor for exclusive access

Published on 07 January 2025 at 02:32

score 2.2k · Answer 12 · 2025-01-07 02:31:35

2.2k

Views

How is a spin lock woken up in Linux/ARM64?

Published on 07 January 2025 at 02:31

score 2.3k · Answer 13 · 2025-01-07 02:32:13

2.3k

Views

When is CLREX actually needed on ARM Cortex M7?

Published on 07 January 2025 at 02:32

score 101 · Answer 14 · 2025-01-07 02:31:33

101

Views

Does lock can avoid lr/sc 'spuriously fail'

Published on 07 January 2025 at 02:31

score 617 · Answer 15 · 2025-01-07 02:35:37

617

Views

How is this a guarantee a value has been atomically updated in ARM?

Published on 07 January 2025 at 02:35

score 39 · Answer 16 · 2025-01-07 02:37:53

39

Views

Can you snoop cache coherence traffic to implement linked-load and store-conditional?

Published on 07 January 2025 at 02:37

score 93 · Answer 17 · 2025-01-07 02:36:21

93

Views

What are costs of disabling interrupts vs LDREX/STREX on Arm Cortex M?

Published on 07 January 2025 at 02:36

score 456 · Answer 18 · 2025-01-07 02:37:27

456

Views

atomic linked-list LIFO in AArch64 assembly, using load or store between ldxr / stxr

Published on 07 January 2025 at 02:37

List Question

ARM LL/SC exclusive access by register width or cache line width?

How does x86 handle store conditional instructions?

How do ldrex / strex make atomic_add in ARM an atomic operation?

Lock-free C++11 example using Load-link/store-conditional to prevent ABA?

In risc-v architecture, how does store conditional instruction realize that the memory is modified?

What' s the advantage of LL/SC when compared with CAS (compare-and-swap)?

ARM Cortex-M4/7: Do regular memory accesses between LDREX/STREX invalidate the exclusive monitor

__sync_add_and_fetch triggers an sError interrupt on raspberry pi 4b

compare-and-swap atomic operation vs Load-link/store-conditional operation

What's 'reservation' in RISC-V's 'lr' instruction?

Implementing global monitor for exclusive access

How is a spin lock woken up in Linux/ARM64?

When is CLREX actually needed on ARM Cortex M7?

Does lock can avoid lr/sc 'spuriously fail'

How is this a guarantee a value has been atomically updated in ARM?

Can you snoop cache coherence traffic to implement linked-load and store-conditional?

What are costs of disabling interrupts vs LDREX/STREX on Arm Cortex M?

atomic linked-list LIFO in AArch64 assembly, using load or store between ldxr / stxr

Trending Questions

Popular # Hahtags

Popular Questions