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18
Devhide
2025-01-07 02:35:39
2.8k
Views
ARM LL/SC exclusive access by register width or cache line width?
Published on
07 January 2025 at 02:35
#assembly
#arm
#atomic
#lock-free
#load-link-store-conditional
1.6k
Views
How does x86 handle store conditional instructions?
Published on
07 January 2025 at 02:32
#x86
#cpu-architecture
#intel
#processors
#load-link-store-conditional
3.4k
Views
How do ldrex / strex make atomic_add in ARM an atomic operation?
Published on
07 January 2025 at 02:35
#linux-kernel
#arm
#atomic
#inline-assembly
#load-link-store-conditional
1.8k
Views
Lock-free C++11 example using Load-link/store-conditional to prevent ABA?
Published on
07 January 2025 at 02:36
#c++
#c++11
#concurrency
#compare-and-swap
#load-link-store-conditional
750
Views
In risc-v architecture, how does store conditional instruction realize that the memory is modified?
Published on
07 January 2025 at 02:38
#assembly
#atomic
#cpu-architecture
#riscv
#load-link-store-conditional
2k
Views
What' s the advantage of LL/SC when compared with CAS (compare-and-swap)?
Published on
07 January 2025 at 02:36
#cpu-architecture
#cas
#compare-and-swap
#load-link-store-conditional
637
Views
ARM Cortex-M4/7: Do regular memory accesses between LDREX/STREX invalidate the exclusive monitor
Published on
07 January 2025 at 02:38
#arm
#atomic
#cortex-m
#stm32f7
#load-link-store-conditional
51
Views
__sync_add_and_fetch triggers an sError interrupt on raspberry pi 4b
Published on
05 January 2025 at 17:23
#memory
#atomic
#arm64
#load-link-store-conditional
#exclusive-lock
6.7k
Views
compare-and-swap atomic operation vs Load-link/store-conditional operation
Published on
07 January 2025 at 02:36
#c++
#atomic
#compare-and-swap
#load-link-store-conditional
2.5k
Views
What's 'reservation' in RISC-V's 'lr' instruction?
Published on
07 January 2025 at 02:32
#atomic
#cpu-architecture
#riscv
#memory-barriers
#load-link-store-conditional
390
Views
Implementing global monitor for exclusive access
Published on
07 January 2025 at 02:32
#arm
#atomic
#memory-barriers
#lock-free
#load-link-store-conditional
2.2k
Views
How is a spin lock woken up in Linux/ARM64?
Published on
07 January 2025 at 02:31
#assembly
#linux-kernel
#arm64
#spinlock
#load-link-store-conditional
2.3k
Views
When is CLREX actually needed on ARM Cortex M7?
Published on
07 January 2025 at 02:32
#arm
#atomic
#cortex-m
#load-link-store-conditional
104
Views
Does lock can avoid lr/sc 'spuriously fail'
Published on
07 January 2025 at 02:31
#assembly
#cpu-architecture
#atomic
#riscv
#load-link-store-conditional
620
Views
How is this a guarantee a value has been atomically updated in ARM?
Published on
07 January 2025 at 02:35
#assembly
#arm
#atomic
#cpu-architecture
#load-link-store-conditional
42
Views
Can you snoop cache coherence traffic to implement linked-load and store-conditional?
Published on
07 January 2025 at 02:37
#caching
#concurrency
#x86-64
#atomic
#load-link-store-conditional
97
Views
What are costs of disabling interrupts vs LDREX/STREX on Arm Cortex M?
Published on
07 January 2025 at 02:36
#arm
#atomic
#interrupt
#cortex-m
#load-link-store-conditional
460
Views
atomic linked-list LIFO in AArch64 assembly, using load or store between ldxr / stxr
Published on
07 January 2025 at 02:37
#c
#inline-assembly
#arm64
#lock-free
#load-link-store-conditional
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