Question

Running .NET on persistent RAM?

score 102 · Answer 1 · 2025-01-07 22:09:30

102

Views

Running .NET on persistent RAM?

Published on 07 January 2025 at 22:09

score 469 · Answer 2 · 2024-12-04 05:22:14

469

Views

How does DC PMM (memory mode) cache coherence behave?

Published on 04 December 2024 at 05:22

score 422 · Answer 3 · 2024-12-04 05:14:37

422

Views

How to read stale values on x86

Published on 04 December 2024 at 05:14

score 226 · Answer 4 · 2024-12-04 05:20:55

226

Views

Does clwb take care of the write in store buffer?

Published on 04 December 2024 at 05:20

score 473 · Answer 5 · 2024-12-16 09:28:33

473

Views

clwb+sfence, can we remove sfence if writes are cache-line aligned?

Published on 16 December 2024 at 09:28

score 1.4k · Answer 6 · 2024-12-04 05:26:40

1.4k

Views

RISC-V instruction to write dirty cache line to next level of cache

Published on 04 December 2024 at 05:26

score 315 · Answer 7 · 2024-12-04 05:26:45

315

Views

Why “movnti” followed by an “sfence” guarantees persistent ordering？

Published on 04 December 2024 at 05:26

score 1.1k · Answer 8 · 2024-12-04 05:30:42

1.1k

Views

Failed mounting to Persistent-Memory-Backed local persisten volume in kubernetes 1.20

Published on 04 December 2024 at 05:30

score 157 · Answer 9 · 2024-12-04 05:22:13

157

Views

How to ensure I am programming on persistent memory

Published on 04 December 2024 at 05:22

score 741 · Answer 10 · 2024-12-17 02:31:32

741

Views

Counting number of allocations into the Write Pending Queue - unexpected low result on NV memory

Published on 17 December 2024 at 02:31

score 547 · Answer 11 · 2024-12-04 05:23:23

547

Views

is there any way get access persistent memory in linux?

Published on 04 December 2024 at 05:23

score 695 · Answer 12 · 2024-12-04 05:30:05

695

Views

How does Linux handle Intel's Optane Persistent Memory Modules under Memory Mode?

Published on 04 December 2024 at 05:30

score 826 · Answer 13 · 2024-12-04 05:30:42

826

Views

how to use non-temporal (streaming) store instructions to store a self-defined struct?

Published on 04 December 2024 at 05:30

score 261 · Answer 14 · 2024-12-04 05:17:58

261

Views

Writing to persistent memory in PCIe

Published on 04 December 2024 at 05:17

score 633 · Answer 15 · 2024-12-04 05:29:28

633

Views

What is the latency of `clwb` and `ntstore` on Intel's Optane Persistent Memory?

Published on 04 December 2024 at 05:29

score 347 · Answer 16 · 2024-12-04 05:28:27

347

Views

(Persistence) ordering of Intel non-temporal stores to the same cache line

Published on 04 December 2024 at 05:28

score 1.5k · Answer 17 · 2024-12-04 05:20:54

1.5k

Views

Intel's CLWB instruction invalidating cache lines

Published on 04 December 2024 at 05:20

score 94 · Answer 18 · 2024-12-04 05:31:45

94

Views

Confused about difference between Intel Optane's Memory Drive Technology (IMDT) and DCPMM memory mode

Published on 04 December 2024 at 05:31

score 312 · Answer 19 · 2024-12-18 13:56:45

312

Views

Do I need to externally call flush if using cuda api to copy from GPU Memory to Persistent Memory?

Published on 18 December 2024 at 13:56

score 779 · Answer 20 · 2024-12-04 05:20:56

779

Views

Is clflush or clflushopt atomic when system crash？

Published on 04 December 2024 at 05:20

List Question

Running .NET on persistent RAM?

How does DC PMM (memory mode) cache coherence behave?

How to read stale values on x86

Does clwb take care of the write in store buffer?

clwb+sfence, can we remove sfence if writes are cache-line aligned?

RISC-V instruction to write dirty cache line to next level of cache

Why “movnti” followed by an “sfence” guarantees persistent ordering？

Failed mounting to Persistent-Memory-Backed local persisten volume in kubernetes 1.20

How to ensure I am programming on persistent memory

Counting number of allocations into the Write Pending Queue - unexpected low result on NV memory

is there any way get access persistent memory in linux?

How does Linux handle Intel's Optane Persistent Memory Modules under Memory Mode?

how to use non-temporal (streaming) store instructions to store a self-defined struct?

Writing to persistent memory in PCIe

What is the latency of `clwb` and `ntstore` on Intel's Optane Persistent Memory?

(Persistence) ordering of Intel non-temporal stores to the same cache line

Intel's CLWB instruction invalidating cache lines

Confused about difference between Intel Optane's Memory Drive Technology (IMDT) and DCPMM memory mode

Do I need to externally call flush if using cuda api to copy from GPU Memory to Persistent Memory?

Is clflush or clflushopt atomic when system crash？

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