Question

Wasm instruction ambiguity for sign-extension?

score 135 · Answer 1 · 2023-10-24T10:09:02.470000

135

Views

Wasm instruction ambiguity for sign-extension?

Published on 24 October 2023 at 10:09

score 48 · Answer 2 · 2023-04-02T01:47:18.650000

48

Views

Understanding if my code takes care of sign extension

Published on 02 April 2023 at 01:47

score 140 · Answer 3 · 2022-11-09T15:49:58.483000

140

Views

MOVSXD operation when operand sizes are equal

Published on 09 November 2022 at 15:49

score 40 · Answer 4 · 2022-08-27T05:54:12.423000

40

Views

Arm64- why all filled with 1 the lower 32bit? Isn't it should be only 1 value?

Published on 27 August 2022 at 05:54

score 129 · Answer 5 · 2022-07-14T16:35:15.817000

129

Views

Convert a char to a uint in c++ in a well defined way for binary data handling

Published on 14 July 2022 at 16:35

score 1.9k · Answer 6 · 2022-04-28T09:36:16.097000

1.9k

Views

What do the `uxtx` and `sxtx` extensions mean for 32-bit AArch64 `adds` instruction?

Published on 28 April 2022 at 09:36

score 377 · Answer 7 · 2021-11-28T18:53:57.337000

377

Views

where does the sign extention happen in lh/lb ( Load Half / Load Byte )?

Published on 28 November 2021 at 18:53

score 295 · Answer 8 · 2021-10-07T13:02:35.783000

295

Views

Assembly movsbq instruction

Published on 07 October 2021 at 13:02

score 904 · Answer 9 · 2021-06-30T22:06:44.670000

904

Views

Sign extend a register to 64-bit (set all bits = sign bit) in Thumb mode

Published on 30 June 2021 at 22:06

score 2.3k · Answer 10 · 2020-12-09T17:26:23.570000

2.3k

Views

Confusion about MIPS I-type instruction sign extend

Published on 09 December 2020 at 17:26

score 357 · Answer 11 · 2020-11-30T16:57:50.543000

357

Views

How to convert int8 to int16 in avr

Published on 30 November 2020 at 16:57

score 412 · Answer 12 · 2020-11-18T11:53:10.463000

412

Views

Zero/Sign extension in assembly without using MOVZX/MOVSX

Published on 18 November 2020 at 11:53

score 639 · Answer 13 · 2020-11-02T23:08:46.480000

639

Views

Sign extension in assembly IA32

Published on 02 November 2020 at 23:08

score 944 · Answer 14 · 2020-10-26T08:48:22.317000

944

Views

needs to understand the meaning behind 0x7fffffff and 0xffffffff80000000 in terms of memory address space layout

Published on 26 October 2020 at 08:48

score 3.2k · Answer 15 · 2020-10-11T06:07:01.280000

3.2k

Views

Why does 2's complement sign extension work by adding copies of the sign bit?

Published on 11 October 2020 at 06:07

score 1.6k · Answer 16 · 2020-08-30T06:04:39.460000

1.6k

Views

x86 assembly - mov and movzx from dword to qword?

Published on 30 August 2020 at 06:04

score 1k · Answer 17 · 2020-06-17T13:24:48.160000

1k

Views

RISC-V: Do 12-bit immediate logical operations operate on the whole register?

Published on 17 June 2020 at 13:24

score 968 · Answer 18 · 2020-05-10T05:10:53.293000

968

Views

What is the effect of the displacement value on the Mod field of the ModRegRm byte?

Published on 10 May 2020 at 05:10

score 316 · Answer 19 · 2020-03-12T11:54:44.217000

316

Views

_mm256_movemask_epi8 to uint64_t

Published on 12 March 2020 at 11:54

score 408 · Answer 20 · 2020-02-24T01:27:45.683000

408

Views

Casting signed to unsigned and vise versa while widening the byte count

Published on 24 February 2020 at 01:27

List Question

Wasm instruction ambiguity for sign-extension?

Understanding if my code takes care of sign extension

MOVSXD operation when operand sizes are equal

Arm64- why all filled with 1 the lower 32bit? Isn't it should be only 1 value?

Convert a char to a uint in c++ in a well defined way for binary data handling

What do the `uxtx` and `sxtx` extensions mean for 32-bit AArch64 `adds` instruction?

where does the sign extention happen in lh/lb ( Load Half / Load Byte )?

Assembly movsbq instruction

Sign extend a register to 64-bit (set all bits = sign bit) in Thumb mode

Confusion about MIPS I-type instruction sign extend

How to convert int8 to int16 in avr

Zero/Sign extension in assembly without using MOVZX/MOVSX

Sign extension in assembly IA32

needs to understand the meaning behind 0x7fffffff and 0xffffffff80000000 in terms of memory address space layout

Why does 2's complement sign extension work by adding copies of the sign bit?

x86 assembly - mov and movzx from dword to qword?

RISC-V: Do 12-bit immediate logical operations operate on the whole register?

What is the effect of the displacement value on the Mod field of the ModRegRm byte?

_mm256_movemask_epi8 to uint64_t

Casting signed to unsigned and vise versa while widening the byte count

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