How can I do a pause of 2Hz in a clock in VHDL?

Question

I'm tecnically new in VHDL, and I need to do a pause of 2Hz or 0.5Hz in VHDL program for a counter project.

On the other hand, i have the following code:

architecture behavior of Counter is
signal q: std_logic_vector(7 downto 0);

begin
process(clock, choose)
  begin

    if clear = '1' then
        q <= q - q;
    else
        if rising_edge(clock) then
            -- when choose is '1', the process if for increment
            if(choose = '1') then
                case incodec is           
                    when "001" => q <= q + 1;
                    when "011" => q <= q + 10;
                    when "111" => q <= q + 11;
                    when others => q <= q;
                end case;
            -- when choose is '0', the process if for decrement
            elsif choose = '0' then
                case incodec is           
                    when "001" => q <= q - 1;
                    when "011" => q <= q - 10;
                    when "111" => q <= q - 11;
                    when others => q <= q;
                end case;
            end if;
        end if;
    end if;
    case q(7 downto 4) is
                                  --  6543210
        when "0000" => hex7 <= "1000000"; --0
        when "0001" => hex7 <= "1111001"; --1
        when "0010" => hex7 <= "0100100"; --2
        when "0011" => hex7 <= "0110000"; --3
        when "0100" => hex7 <= "0011001"; --4
        when "0101" => hex7 <= "0010010"; --5
        when "0110" => hex7 <= "0000010"; --6
        when "0111" => hex7 <= "1111000"; --7
        when "1000" => hex7 <= "0000000"; --8
        when "1001" => hex7 <= "0010000"; --9
        when "1010" => hex7 <= "0001000"; --10/A
        when "1011" => hex7 <= "0000011"; --11/B/b
        when "1100" => hex7 <= "1000110"; --12/C
        when "1101" => hex7 <= "0100001"; --13/D/d
        when "1110" => hex7 <= "0000110"; --14/E
        when "1111" => hex7 <= "0001110"; --15/F
        when others => hex7 <= "0111111"; -- -
    end case;

    case q(3 downto 0) is
                                  --  6543210
        when "0000" => hex6 <= "1000000"; --0
        when "0001" => hex6 <= "1111001"; --1
        when "0010" => hex6 <= "0100100"; --2
        when "0011" => hex6 <= "0110000"; --3
        when "0100" => hex6 <= "0011001"; --4
        when "0101" => hex6 <= "0010010"; --5
        when "0110" => hex6 <= "0000010"; --6
        when "0111" => hex6 <= "1111000"; --7
        when "1000" => hex6 <= "0000000"; --8
        when "1001" => hex6 <= "0010000"; --9
        when "1010" => hex6 <= "0001000"; --10/A
        when "1011" => hex6 <= "0000011"; --11/B/b
        when "1100" => hex6 <= "1000110"; --12/C
        when "1101" => hex6 <= "0100001"; --13/D/d
        when "1110" => hex6 <= "0000110"; --14/E
        when "1111" => hex6 <= "0001110"; --15/F
        when others => hex6 <= "0111111"; -- -
    end case;
end behavior

When the program compile show the following error:

Error (10818): Can't infer register for "q[0]" at Counter.vhd(28) because it does not hold its value outside the clock edge I don't know what is means

Help me please :(

Answer 1

Your code contains multiple mistakes:

• Don't use the Synopsys packages to do arithmetic operations.
  Use package numeric_std and types signed and/or unsigned instead.
• q represents state and will be synthesized as flip-flops.
  So on an FPGA technology, initialize them: := (others => '0')
• clear is an asynchronous signal, so list it in the sensitivity list.
• choose is a synchronous signal, so don't list it in the sensitivity list.
• When you want to add numbers 1,2,3 then use proper integer literals or specify your literal explicitly as binary. The default is decimal.
• Using variables will shorten your code by eliminating duplication.
• Clearing q should be done by assigning all zeros with an aggregate: (others => '0').
• A for loop and another variable can further reduce your code and remove another big section of duplicated code.
• User variable hex will also remove an additional register stage, that is most likely not intended by most designers.
• You commented you segment names of the 7-segment display 6543210, but segments are usually named GFEDCBA.
• You should put your 7-segment decoder into a separate entity or function to increase reuseability.
• Your 7-segment display code is low-active, but designers should write high-active code. The low-activeness is due to the board or display design and not the responsibility of the decoder. Inversion can be done when assigning hex to hex7.

Here is the improved code:

library IEEE;
use     IEEE.std_logic_1164.all;
use     IEEE.numeric_std.all;


entity Counter is
    -- ...
end entity;


architecture behavior of Counter is
    signal q : unsigned(7 downto 0) := (others => '0');
begin
    process(clock, clear)
        variable decoded : positive;
        variable hex     : std_logic_vector(13 downto 0);
    begin
        case incodec is           
            when "001" =>  decoded := 1;
            when "011" =>  decoded := 2;
            when "111" =>  decoded := 3;
            when others => decoded := 0;
        end case;

        if clear = '1' then
            q <= (others => '0');
        elsif rising_edge(clock) then
            if(choose = '1') then     -- when choose is '1', the process if for increment
                q <= q + decoded;
            elsif (choose = '0') then -- when choose is '0', the process if for decrement
                q <= q - decoded;
            end if;
        end if;

        for i in 0 to 1 loop
            case q(i*4+7 downto i*4) is            --  6543210
                when "0000" => hex(i*7+6 downto i*7) := "1000000"; --0
                when "0001" => hex(i*7+6 downto i*7) := "1111001"; --1
                when "0010" => hex(i*7+6 downto i*7) := "0100100"; --2
                when "0011" => hex(i*7+6 downto i*7) := "0110000"; --3
                when "0100" => hex(i*7+6 downto i*7) := "0011001"; --4
                when "0101" => hex(i*7+6 downto i*7) := "0010010"; --5
                when "0110" => hex(i*7+6 downto i*7) := "0000010"; --6
                when "0111" => hex(i*7+6 downto i*7) := "1111000"; --7
                when "1000" => hex(i*7+6 downto i*7) := "0000000"; --8
                when "1001" => hex(i*7+6 downto i*7) := "0010000"; --9
                when "1010" => hex(i*7+6 downto i*7) := "0001000"; --10/A
                when "1011" => hex(i*7+6 downto i*7) := "0000011"; --11/b
                when "1100" => hex(i*7+6 downto i*7) := "1000110"; --12/C
                when "1101" => hex(i*7+6 downto i*7) := "0100001"; --13/d
                when "1110" => hex(i*7+6 downto i*7) := "0000110"; --14/E
                when "1111" => hex(i*7+6 downto i*7) := "0001110"; --15/F
                when others => hex(i*7+6 downto i*7) := "0111111"; -- -
            end case;
        end loop;

        hex7 <= hex(13 downto 7);
        hex6 <= hex(6 downto 0);
    end process;
end architecture;