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20
Devhide
2024-12-28 22:22:33
2.8k
Views
Altera UART IP Core
Published on
28 December 2024 at 22:22
#fpga
#uart
#intel-fpga
#quartus
#qsys
221
Views
Emulating altera bitstream
Published on
06 January 2025 at 23:10
#fpga
#emulation
#intel-fpga
199
Views
Mixer-Unit on Altera DE2-115 Cyclone IV
Published on
06 January 2025 at 23:11
#vhdl
#fpga
#intel-fpga
#cyclone
834
Views
Memory mapped ADC on DE1-SoC using HPS (hard-core processor)
Published on
05 January 2025 at 06:48
#c
#fpga
#intel-fpga
#adc
#peripherals
866
Views
How to see the content of the ON-CHIP RAM of my design in DE1-SOC FPGA?
Published on
06 January 2025 at 23:16
#memory
#fpga
#ram
#intel-fpga
#synthesis
589
Views
Does Quartus II support line.all?
Published on
06 January 2025 at 23:12
#vhdl
#xilinx
#intel-fpga
#quartus
2.7k
Views
Verilog FIR filter
Published on
28 December 2024 at 22:07
#filter
#verilog
#intel-fpga
1.8k
Views
vhdl manual clock hour set
Published on
06 January 2025 at 23:10
#vhdl
#clock
#intel-fpga
410
Views
C to Fpga error with LCD under Altera DE2-70 board
Published on
27 December 2024 at 22:44
#intel-fpga
#hardware-interface
#systemc
7.6k
Views
How to generate delay in verilog using Counter for Synthesis and call inside Always block?
Published on
06 January 2025 at 23:18
#verilog
#fpga
#xilinx
#system-verilog
#intel-fpga
340
Views
Automated test runs with Altera Quartus
Published on
06 January 2025 at 23:11
#testing
#continuous-integration
#fpga
#intel-fpga
4.2k
Views
"No such file or directory" when running app on linux arm target
Published on
06 January 2025 at 23:16
#linux
#gcc
#intel-fpga
1k
Views
Can I use Modelsim license for Student Edition 10.6 for Altera Modelsim 16.0 edition?
Published on
06 January 2025 at 23:17
#modelsim
#intel-fpga
7.7k
Views
VHDL buffer variable vs out variable
Published on
06 January 2025 at 23:12
#vhdl
#fpga
#intel-fpga
645
Views
How can I do a pause of 2Hz in a clock in VHDL?
Published on
06 January 2025 at 23:13
#vhdl
#clock
#intel-fpga
2.6k
Views
Driving bidirectional lines in Verilog
Published on
06 January 2025 at 23:11
#embedded
#verilog
#fpga
#hdl
#intel-fpga
239
Views
How to develop this algorithm?
Published on
06 January 2025 at 23:10
#c
#assembly
#fpga
#intel-fpga
#nios
1.3k
Views
Polling with C and assembly for Nios 2
Published on
06 January 2025 at 23:11
#c
#assembly
#fpga
#intel-fpga
#nios
10.1k
Views
Unable to lock chain (Insufficient port permissions)
Published on
06 January 2025 at 23:13
#linux
#embedded
#embedded-linux
#intel-fpga
21.6k
Views
4 bit adder in vhdl
Published on
28 December 2024 at 22:22
#vhdl
#intel-fpga
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