How can I make a ternary condition in SpinalHDL?

Question

I would like to make a ternary condition in SpinalHDL as a ternary assignment in Verilog:

e.g.

wire my_condition = (this == that);

wire [1:0] my_ternary_wire = my_condition ? 2'b10 : 2'b01;

desired SpinalHDL code:

val myCondition = this === that

val myTernaryWire = myCondition ? B(3) : B(1)

Answer 1

I just saw it is possible to use:

val myCondition = this === that

val myTernaryWire = myCondition ? B(3) | B(1)

just changing : to |