How can i set a define in a makefile with multiple executables

Question

I am trying to compile a game (program1.exe) and editor(program2.exe) which share many of thesame source files, currently i use a #define in the source files, but i'd like to automate this if its even possible and move this to the makefile.

The text below is a short example of the situation.

Makefile:

all: Program1.exe

CC=gcc
CFLAGS=-Wall

OBJECTS= .obj/main.o .obj/test.o .obj/example.o\


Program1.exe:       $(OBJECTS)
    $(CC) -o "$@" $^

Program2.exe:       $(OBJECTS)
    $(CC) -o "$@" $^
    
    
    
.obj/main.o:            main.c      test.h example.h
$(CC) -c -o $@ $< $(CFLAGS)

.obj/test.o:            test.c          test.h
$(CC) -c -o $@ $< $(CFLAGS)

.obj/example.o: example.c   example.h
$(CC) -c -o $@ $< $(CFLAGS)


two: Program2.exe

Basically running 'make' compiles Program1.exe, while 'make two' will compile Program2.exe I wonna be able to pass a define and only when compiling program2.exe

Expected result is this: When i compile Program1 (make), i want the object files to move to .obj/ (this works) When i compile Program2 (make two) i want the object files to move to subdirectory .obj/editor/ and i need to pass a define -DEDITOR so the source files compile certain parts of the source code.

When i add the following to the makefile:

CFLAGS+= -DEDITOR

It actually works, but it compiles both programs with that flag, which is not what i want.

I also tried making a copy of all the objects with a different subdirectory name:

EOBJECTS= .obj/editor/main.o .obj/editor/test.o .obj/editor/example.c\

.obj/editor/example.c   example.h
$(CC) -c -o $@ $< $(CFLAGS)

Then also adding:

.obj/editor/%.o: CFLAGS += -DEDITOR

Program2.exe:       $(EOBJECTS)
    $(CC) -o "$@" $^

This actually works but messes up my makefile, it has an insane amount of lines and is not very good for upkeeping the file towards the future, since i have each object duplicated.

I also tried a common solution on the internet, but this does not apply the define to my source files for some reason:

Program2.exe:       $(OBJECTS)
    $(CC) -DEDITOR -o "$@" $^

Is there a way to add a define to only one out of multiple make targets and make a copy of the current object files, so i can compile both programs individually who share thesame source?