I encountered an issue about bad memory allocation while compiling large chisel hardware design to C++ model using verilator backend.
When i want to built a large PE design (36x36 for example), I write my code like this
PEArray = Seq.fill(height)(Seq.fill(width)(Module new PE).io)
and the verilator would crash then throw
terminate called after throwing an instance of 'std::bad_alloc' what(): std::bad_alloc
Something like the memory not enough cause this problem, is there any memory-efficiency Chisel3 built-in function or other ways to solve this problem?