How to interface Red Pitaya FPGA with server code using Vivado

Question

I have currently made a GUI in PyQT5 (the client) and have made a server using C code. The goal is to send input from the GUI to the server, and then the server interfacing with the FPGA to produce a signal that I will read from an oscilloscope (I am using a Red Pitaya as my board). I have currently made the GUI and am able to send data to the server which it successfully receives (while the server running on the red pitaya), however, I am unsure on how to use Vivado 2019.1 to send the data received by the server to a specific input I have created in my block diagram. Im assuming

I have to assign the input pin with one of the red pitaya ports, but unsure where/how to do that in Vivado or in C server.

Basically, can anyone point me in the direction of how to interface my C server code with the input of my block diagram in Vivado.

My red pitaya board is connected to my PC via ethernet and has its own IP address that I use to run its linux server in PuTTY. I run the server in the PuTTY shell using gcc.

EDIT: Sorry about the ambiguity. What I am trying to do is to load the .bit file generated by Vivado to my Red Pitaya, and then run my server (TCP/IP) in the red pitaya linux shell (using PuTTY). The point being, I want to be able to send data I input from the GUI to the server (which will be running on the red pitaya's linux server) and then that data is sent to an input that was made in my Vivado project which would be on the .bit file (the input) that was loaded to the board.

If what Im saying is a unclear or I'm approaching this in the wrong way please let me know!

Answer 1

My question is how to write the data in the server to that 32-bit input on the board.

A great deal of trouble with answering your question is to get our nomenclature (what we call the things we talk about) sorted out.

Normally when we talk about an 'input' and 'FPGA code' that would mean an input port on the FPGA. In input implies that it takes data from an external source. Your CPU can not send data to that input.

maybe you refer to a 'block' on the FPGA which performs a function and which can be accessed from the CPU. (As that 'block has a read/write port which is connected to the CPU bus.) That is normally called a 'peripheral'.

The way you ask your question makes me suspect that somebody else has made such a peripheral. Or you are even one step further back and you still need to make your peripheral. Maybe you can show part of the diagram you talk about.

If you already have a peripheral you can open the 'address' tab which is shown next to the tab which shows your 'diagram'. In there you can find a list of all peripherals and the CPU address you need to use to access them.

Besides the address you should know how the peripheral works. If there are internal register and what they do. In short: However made the peripheral should have made a manual for it.

If you not even have a peripheral but only a (floating, unconnected) input port we/I can't help you as it would take weeks to teach you HDL and how to make a peripheral with an AXI bus.

Answer 2

Here I am assuming the ARM part of the FPGA SoC (your board most probably has Xilinx Zynq 7010 SoC or something similar) reachable now (using ethernet connection).

Firstly, you need to create a custom IP core for your block to make your custom block conform with AXI4 protocol (there is a tool in Vivado which can generate the interface code automatically, you just need to correctly instantiate your module and make proper port connections). Using the block design tool (in Vivado), you need to properly connect your custom IP to the processor IP core (connect AXI master of the processor to the AXI slave of your custom IP core), the tool helps you to make the proper connections.

A header file for your custom design can be automatically generated (for properly addressing). You can use the generated header to write a C code that gets instructions coming from the server, converts to ones that your custom IP can understand and sends them to correct address to be able to control your custom block correctly.

EDIT 1: These YouTube tutorials might be helpful for you: 1, 2, 3

Answer 3

The easiest way to send data from the Zynq PS (processing system, Linux) to the Zynq PL (programable logic, FPGA) is by using an AXI GPIO.

Inside your Vivado design you have to:

• Instantiate an AXI GPIO, configure its width and its direction (read or write).
• I recommend to use the connection automation tool of Vivado to correctly wire the AXI GPIO to the Zynq processing system.
• Look at the address editor in Vivado and write down the AXI address of your GPIO port.

In your C/C++ code you have to:

• Make a memory mapping and assign a variable to the memory address of your AXI GPIO.
• Read/write to that address.

Example:

I have recently built a graphical design tool for programming the FPGA of your Redpitaya (DSPsandbox-Canvas), it includes AXI GPIOs and C code for accessing them over the PS.

You can download the soure code of the project here. If you open the Vivado Project /Zynq_7010/Zynq_PL/Canvas.xpr, you will see that the communication to the Zynq PS is done through the above mentioned AXI GPIOs. In order to access these GPIOs within Linux, I use /Zynq_7010/Zynq_PS/constantsLoader.c, which performs the memory mapping, reads a set of .txt files and configures the GPIOs accordingly. I am sure you can adapt this code for placing it inside your TCP server.