How to interpret this Xtensa exception info?

Question

I am debugging on a Xtensa board. But I don't have enough knowledge or reference materials to interpret below exception info.

Could anyone familiar with Xtensa arch shed some light? Or point me to the docs explaining the Xtensa registers.

I only have a xtensa_lx7_data_book. Still digging into it...

>>>> FATAL EXCEPTION
>>>> CPU 0 EXCCAUSE 12 (instr PIF data error)
>>>>  PC 0x1 VADDR (nil)
>>>>  PS 0x60620
>>>>    (INTLEVEL:0 EXCM: 0 UM:1 RING:0 WOE:1 OWB:6 CALLINC:2)
>>>>  A0 0xbe0115f2  SP 0xbe01d8f0  A2 0xbe01c8d8  A3 0x1
>>>>  A4 0x9e022dbc  A5 0x9e0225b8  A6 0x1  A7 (nil)
>>>>  A8 0xbe013a88  A9 0xbe01d8a0 A10 (nil) A11 (nil)
>>>> A12 (nil) A13 0x1 A14 0xbe01d8ec A15 0x60522
>>>> LBEG (nil) LEND (nil) LCOUNT (nil)
>>>> SAR 0x5

ADD 1

Some findings so far:

• A0:return address
• A1: stack pointer, aka. SP
• PC: Program Counter
• PS: Program State (I guess)

Answer 1

According to the value of registers PC and EXCCAUSE the CPU attempted to execute code at address 0x1 and couldn't fetch an instruction from that address.

All registers mentioned in the exception info are the core xtensa registers and are described in the xtensa ISA book.